On 3/26/21 12:46 PM, Jason Gunthorpe wrote:
On Fri, Mar 26, 2021 at 10:08:09AM +0100, Thomas Hellström (Intel) wrote:
On 3/25/21 7:24 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 07:13:33PM +0100, Thomas Hellström (Intel) wrote:
On 3/25/21 6:55 PM, Jason Gunthorpe wrote:
On Thu, Mar 2
On Fri, Mar 26, 2021 at 10:08:09AM +0100, Thomas Hellström (Intel) wrote:
>
> On 3/25/21 7:24 PM, Jason Gunthorpe wrote:
> > On Thu, Mar 25, 2021 at 07:13:33PM +0100, Thomas Hellström (Intel) wrote:
> > > On 3/25/21 6:55 PM, Jason Gunthorpe wrote:
> > > > On Thu, Mar 25, 2021 at 06:51:26PM +0100,
On 3/25/21 7:24 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 07:13:33PM +0100, Thomas Hellström (Intel) wrote:
On 3/25/21 6:55 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 06:51:26PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 9:25 PM, Dave Hansen wrote:
On 3/24/21 1:22 PM
On 3/25/21 7:24 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 07:13:33PM +0100, Thomas Hellström (Intel) wrote:
On 3/25/21 6:55 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 06:51:26PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 9:25 PM, Dave Hansen wrote:
On 3/24/21 1:22 PM
On Thu, Mar 25, 2021 at 07:13:33PM +0100, Thomas Hellström (Intel) wrote:
>
> On 3/25/21 6:55 PM, Jason Gunthorpe wrote:
> > On Thu, Mar 25, 2021 at 06:51:26PM +0100, Thomas Hellström (Intel) wrote:
> > > On 3/24/21 9:25 PM, Dave Hansen wrote:
> > > > On 3/24/21 1:22 PM, Thomas Hellström (Intel) w
On 3/25/21 6:55 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 06:51:26PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 9:25 PM, Dave Hansen wrote:
On 3/24/21 1:22 PM, Thomas Hellström (Intel) wrote:
We also have not been careful at *all* about how _PAGE_BIT_SOFTW* are
used. It's qu
On Thu, Mar 25, 2021 at 06:51:26PM +0100, Thomas Hellström (Intel) wrote:
>
> On 3/24/21 9:25 PM, Dave Hansen wrote:
> > On 3/24/21 1:22 PM, Thomas Hellström (Intel) wrote:
> > > > We also have not been careful at *all* about how _PAGE_BIT_SOFTW* are
> > > > used. It's quite possible we can encod
On 3/24/21 9:25 PM, Dave Hansen wrote:
On 3/24/21 1:22 PM, Thomas Hellström (Intel) wrote:
We also have not been careful at *all* about how _PAGE_BIT_SOFTW* are
used. It's quite possible we can encode another use even in the
existing bits.
Personally, I'd just try:
#define _PAGE_BIT_SOFTW5
On Thu, Mar 25, 2021 at 02:54:31PM +0100, Christian König wrote:
> > The goal is to optimize large page size usage in the page tables.
> >
> > There are three critera that impact this:
> > 1) The possible CPU page table sizes
> > 2) The useful contiguity the device can create in its iomemory
Am 25.03.21 um 14:33 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 02:26:50PM +0100, Christian König wrote:
Am 25.03.21 um 14:17 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 02:05:14PM +0100, Christian König wrote:
Am 25.03.21 um 13:42 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 0
On Thu, Mar 25, 2021 at 02:26:50PM +0100, Christian König wrote:
> Am 25.03.21 um 14:17 schrieb Jason Gunthorpe:
> > On Thu, Mar 25, 2021 at 02:05:14PM +0100, Christian König wrote:
> > >
> > > Am 25.03.21 um 13:42 schrieb Jason Gunthorpe:
> > > > On Thu, Mar 25, 2021 at 01:09:14PM +0100, Christia
Hi,
On 3/25/21 2:02 PM, Christian König wrote:
Am 25.03.21 um 13:36 schrieb Thomas Hellström (Intel):
On 3/25/21 1:09 PM, Christian König wrote:
Am 25.03.21 um 13:01 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 12:53:15PM +0100, Thomas Hellström (Intel)
wrote:
Nope. The point here wa
Am 25.03.21 um 14:17 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 02:05:14PM +0100, Christian König wrote:
Am 25.03.21 um 13:42 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 01:09:14PM +0100, Christian König wrote:
Am 25.03.21 um 13:01 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at
On Thu, Mar 25, 2021 at 02:05:14PM +0100, Christian König wrote:
>
>
> Am 25.03.21 um 13:42 schrieb Jason Gunthorpe:
> > On Thu, Mar 25, 2021 at 01:09:14PM +0100, Christian König wrote:
> > > Am 25.03.21 um 13:01 schrieb Jason Gunthorpe:
> > > > On Thu, Mar 25, 2021 at 12:53:15PM +0100, Thomas He
Am 25.03.21 um 13:42 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 01:09:14PM +0100, Christian König wrote:
Am 25.03.21 um 13:01 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 12:53:15PM +0100, Thomas Hellström (Intel) wrote:
Nope. The point here was that in this case, to make sure mm
Am 25.03.21 um 13:36 schrieb Thomas Hellström (Intel):
On 3/25/21 1:09 PM, Christian König wrote:
Am 25.03.21 um 13:01 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 12:53:15PM +0100, Thomas Hellström (Intel)
wrote:
Nope. The point here was that in this case, to make sure mmap uses the
On Thu, Mar 25, 2021 at 01:09:14PM +0100, Christian König wrote:
> Am 25.03.21 um 13:01 schrieb Jason Gunthorpe:
> > On Thu, Mar 25, 2021 at 12:53:15PM +0100, Thomas Hellström (Intel) wrote:
> >
> > > Nope. The point here was that in this case, to make sure mmap uses the
> > > correct VA to give u
On 3/25/21 1:09 PM, Christian König wrote:
Am 25.03.21 um 13:01 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 12:53:15PM +0100, Thomas Hellström (Intel)
wrote:
Nope. The point here was that in this case, to make sure mmap uses the
correct VA to give us a reasonable chance of alignement,
Am 25.03.21 um 13:01 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 12:53:15PM +0100, Thomas Hellström (Intel) wrote:
Nope. The point here was that in this case, to make sure mmap uses the
correct VA to give us a reasonable chance of alignement, the driver might
need to be aware of and do tri
On Thu, Mar 25, 2021 at 12:53:15PM +0100, Thomas Hellström (Intel) wrote:
> Nope. The point here was that in this case, to make sure mmap uses the
> correct VA to give us a reasonable chance of alignement, the driver might
> need to be aware of and do trickery with the huge page-table-entry sizes
On 3/25/21 12:30 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 10:51:35AM +0100, Thomas Hellström (Intel) wrote:
Please explain that further. Why do we need the mmap lock to insert PMDs
but not when insert PTEs?
We don't. But once you've inserted a PMD directory you can't remove it
unle
On Thu, Mar 25, 2021 at 10:51:35AM +0100, Thomas Hellström (Intel) wrote:
> > Please explain that further. Why do we need the mmap lock to insert PMDs
> > but not when insert PTEs?
>
> We don't. But once you've inserted a PMD directory you can't remove it
> unless you have the mmap lock (and prob
On 3/25/21 9:27 AM, Christian König wrote:
Am 25.03.21 um 08:48 schrieb Thomas Hellström (Intel):
On 3/25/21 12:14 AM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 09:07:53PM +0100, Thomas Hellström (Intel)
wrote:
On 3/24/21 7:31 PM, Christian König wrote:
Am 24.03.21 um 17:38 schrieb J
On Thu, Mar 25, 2021 at 8:50 AM Christian König
wrote:
>
> Am 25.03.21 um 00:14 schrieb Jason Gunthorpe:
> > On Wed, Mar 24, 2021 at 09:07:53PM +0100, Thomas Hellström (Intel) wrote:
> >> On 3/24/21 7:31 PM, Christian König wrote:
> >>>
> >>> Am 24.03.21 um 17:38 schrieb Jason Gunthorpe:
> On
Am 25.03.21 um 08:48 schrieb Thomas Hellström (Intel):
On 3/25/21 12:14 AM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 09:07:53PM +0100, Thomas Hellström (Intel)
wrote:
On 3/24/21 7:31 PM, Christian König wrote:
Am 24.03.21 um 17:38 schrieb Jason Gunthorpe:
On Wed, Mar 24, 2021 at 04:50
Am 25.03.21 um 00:14 schrieb Jason Gunthorpe:
On Wed, Mar 24, 2021 at 09:07:53PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 7:31 PM, Christian König wrote:
Am 24.03.21 um 17:38 schrieb Jason Gunthorpe:
On Wed, Mar 24, 2021 at 04:50:14PM +0100, Thomas Hellström (Intel)
wrote:
On 3/24/2
On 3/25/21 12:14 AM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 09:07:53PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 7:31 PM, Christian König wrote:
Am 24.03.21 um 17:38 schrieb Jason Gunthorpe:
On Wed, Mar 24, 2021 at 04:50:14PM +0100, Thomas Hellström (Intel)
wrote:
On 3/24/2
On Wed, Mar 24, 2021 at 09:07:53PM +0100, Thomas Hellström (Intel) wrote:
>
> On 3/24/21 7:31 PM, Christian König wrote:
> >
> >
> > Am 24.03.21 um 17:38 schrieb Jason Gunthorpe:
> > > On Wed, Mar 24, 2021 at 04:50:14PM +0100, Thomas Hellström (Intel)
> > > wrote:
> > > > On 3/24/21 2:48 PM, Jas
On 3/24/21 1:22 PM, Thomas Hellström (Intel) wrote:
>> We also have not been careful at *all* about how _PAGE_BIT_SOFTW* are
>> used. It's quite possible we can encode another use even in the
>> existing bits.
>>
>> Personally, I'd just try:
>>
>> #define _PAGE_BIT_SOFTW5 57 /* availab
On 3/24/21 5:34 PM, Dave Hansen wrote:
On 3/24/21 3:05 AM, Thomas Hellström (Intel) wrote:
Yes, I agree. Seems like the special (SW1) is available also for huge
page table entries on x86 AFAICT, although just not implemented.
Otherwise the SW bits appear completely used up.
Although the _PAGE
On 3/24/21 7:31 PM, Christian König wrote:
Am 24.03.21 um 17:38 schrieb Jason Gunthorpe:
On Wed, Mar 24, 2021 at 04:50:14PM +0100, Thomas Hellström (Intel)
wrote:
On 3/24/21 2:48 PM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 02:35:38PM +0100, Thomas Hellström (Intel)
wrote:
In an id
Am 24.03.21 um 17:38 schrieb Jason Gunthorpe:
On Wed, Mar 24, 2021 at 04:50:14PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 2:48 PM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 02:35:38PM +0100, Thomas Hellström (Intel) wrote:
In an ideal world the creation/destruction of page ta
On Wed, Mar 24, 2021 at 04:50:14PM +0100, Thomas Hellström (Intel) wrote:
>
> On 3/24/21 2:48 PM, Jason Gunthorpe wrote:
> > On Wed, Mar 24, 2021 at 02:35:38PM +0100, Thomas Hellström (Intel) wrote:
> >
> > > > In an ideal world the creation/destruction of page table levels would
> > > > by dynam
On 3/24/21 3:05 AM, Thomas Hellström (Intel) wrote:
> Yes, I agree. Seems like the special (SW1) is available also for huge
> page table entries on x86 AFAICT, although just not implemented.
> Otherwise the SW bits appear completely used up.
Although the _PAGE_BIT_SOFTW* bits are used up, there's
On 3/24/21 2:48 PM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 02:35:38PM +0100, Thomas Hellström (Intel) wrote:
In an ideal world the creation/destruction of page table levels would
by dynamic at this point, like THP.
Hmm, but I'm not sure what problem we're trying to solve by changing
On Wed, Mar 24, 2021 at 02:35:38PM +0100, Thomas Hellström (Intel) wrote:
> > In an ideal world the creation/destruction of page table levels would
> > by dynamic at this point, like THP.
>
> Hmm, but I'm not sure what problem we're trying to solve by changing the
> interface in this way?
We are
On 3/24/21 1:41 PM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 01:35:17PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 1:24 PM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 10:56:43AM +0100, Daniel Vetter wrote:
On Tue, Mar 23, 2021 at 06:06:53PM +0100, Thomas Hellström (Intel) wr
On Wed, Mar 24, 2021 at 01:35:17PM +0100, Thomas Hellström (Intel) wrote:
>
> On 3/24/21 1:24 PM, Jason Gunthorpe wrote:
> > On Wed, Mar 24, 2021 at 10:56:43AM +0100, Daniel Vetter wrote:
> > > On Tue, Mar 23, 2021 at 06:06:53PM +0100, Thomas Hellström (Intel) wrote:
> > > > On 3/23/21 5:37 PM, Ja
On 3/24/21 1:24 PM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 10:56:43AM +0100, Daniel Vetter wrote:
On Tue, Mar 23, 2021 at 06:06:53PM +0100, Thomas Hellström (Intel) wrote:
On 3/23/21 5:37 PM, Jason Gunthorpe wrote:
On Tue, Mar 23, 2021 at 05:34:51PM +0100, Thomas Hellström (Intel) wr
On Wed, Mar 24, 2021 at 10:56:43AM +0100, Daniel Vetter wrote:
> On Tue, Mar 23, 2021 at 06:06:53PM +0100, Thomas Hellström (Intel) wrote:
> >
> > On 3/23/21 5:37 PM, Jason Gunthorpe wrote:
> > > On Tue, Mar 23, 2021 at 05:34:51PM +0100, Thomas Hellström (Intel) wrote:
> > >
> > > > > > @@ -210,6
On 3/24/21 10:58 AM, Daniel Vetter wrote:
On Tue, Mar 23, 2021 at 09:42:18PM +0100, Thomas Hellström (Intel) wrote:
On 3/23/21 8:52 PM, Williams, Dan J wrote:
On Sun, 2021-03-21 at 19:45 +0100, Thomas Hellström (Intel) wrote:
TTM sets up huge page-table-entries both to system- and device
mem
On Tue, Mar 23, 2021 at 09:42:18PM +0100, Thomas Hellström (Intel) wrote:
>
> On 3/23/21 8:52 PM, Williams, Dan J wrote:
> > On Sun, 2021-03-21 at 19:45 +0100, Thomas Hellström (Intel) wrote:
> > > TTM sets up huge page-table-entries both to system- and device
> > > memory,
> > > and we don't want
On Tue, Mar 23, 2021 at 06:06:53PM +0100, Thomas Hellström (Intel) wrote:
>
> On 3/23/21 5:37 PM, Jason Gunthorpe wrote:
> > On Tue, Mar 23, 2021 at 05:34:51PM +0100, Thomas Hellström (Intel) wrote:
> >
> > > > > @@ -210,6 +211,20 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct
> > > > > vm_fa
On 3/23/21 8:52 PM, Williams, Dan J wrote:
On Sun, 2021-03-21 at 19:45 +0100, Thomas Hellström (Intel) wrote:
TTM sets up huge page-table-entries both to system- and device
memory,
and we don't want gup to assume there are always valid backing struct
pages for these. For PTEs this is handled b
On Sun, 2021-03-21 at 19:45 +0100, Thomas Hellström (Intel) wrote:
> TTM sets up huge page-table-entries both to system- and device
> memory,
> and we don't want gup to assume there are always valid backing struct
> pages for these. For PTEs this is handled by setting the pte_special
> bit,
> but f
On 3/23/21 5:37 PM, Jason Gunthorpe wrote:
On Tue, Mar 23, 2021 at 05:34:51PM +0100, Thomas Hellström (Intel) wrote:
@@ -210,6 +211,20 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault
*vmf,
if ((pfn & (fault_page_size - 1)) != 0)
goto out_fallback;
+ /
On Tue, Mar 23, 2021 at 01:37:15PM -0300, Jason Gunthorpe wrote:
> Isn't the devmap PTE flag arch optional? Does this fall back to not
> using huge pages on arches that don't support it?
>
> Also, I feel like this code to install "pte_special" huge pages does
> not belong in the drm subsystem..
I
On Tue, Mar 23, 2021 at 05:34:51PM +0100, Thomas Hellström (Intel) wrote:
> > > @@ -210,6 +211,20 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct
> > > vm_fault *vmf,
> > > if ((pfn & (fault_page_size - 1)) != 0)
> > > goto out_fallback;
> > > + /*
> > > + * Huge en
Hi,
On 3/23/21 12:34 PM, Daniel Vetter wrote:
On Sun, Mar 21, 2021 at 07:45:28PM +0100, Thomas Hellström (Intel) wrote:
TTM sets up huge page-table-entries both to system- and device memory,
and we don't want gup to assume there are always valid backing struct
pages for these. For PTEs this is
On 3/23/21 2:52 PM, Jason Gunthorpe wrote:
On Sun, Mar 21, 2021 at 07:45:28PM +0100, Thomas Hellström (Intel) wrote:
diff --git a/mm/gup.c b/mm/gup.c
index e40579624f10..1b6a127f0bdd 100644
+++ b/mm/gup.c
@@ -1993,6 +1993,17 @@ static void __maybe_unused undo_dev_pagemap(int *nr, int
nr_start
On Sun, Mar 21, 2021 at 07:45:28PM +0100, Thomas Hellström (Intel) wrote:
> diff --git a/mm/gup.c b/mm/gup.c
> index e40579624f10..1b6a127f0bdd 100644
> +++ b/mm/gup.c
> @@ -1993,6 +1993,17 @@ static void __maybe_unused undo_dev_pagemap(int *nr,
> int nr_start,
> }
>
> #ifdef CONFIG_ARCH_HAS_P
On Sun, Mar 21, 2021 at 07:45:28PM +0100, Thomas Hellström (Intel) wrote:
> TTM sets up huge page-table-entries both to system- and device memory,
> and we don't want gup to assume there are always valid backing struct
> pages for these. For PTEs this is handled by setting the pte_special bit,
> bu
TTM sets up huge page-table-entries both to system- and device memory,
and we don't want gup to assume there are always valid backing struct
pages for these. For PTEs this is handled by setting the pte_special bit,
but for the huge PUDs and PMDs, we have neither pmd_special nor
pud_special. Normall
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