Re: [RFC PATCH] ACPI/PCI: Fix bus range comparation in pci_mcfg_lookup

2017-01-03 Thread Zhou Wang
On 2017/1/3 20:00, Lorenzo Pieralisi wrote: > On Thu, Dec 22, 2016 at 05:07:43PM +0800, Zhou Wang wrote: >> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for >> each >> host bridge should be in the coverage of bus range of related PCIe segment. >> >> This patch will suppo

Re: [RFC PATCH] ACPI/PCI: Fix bus range comparation in pci_mcfg_lookup

2017-01-03 Thread Lorenzo Pieralisi
On Thu, Dec 22, 2016 at 05:07:43PM +0800, Zhou Wang wrote: > Multiple PCIe host bridges may exists in one PCIe segment. So bus range for > each > host bridge should be in the coverage of bus range of related PCIe segment. > > This patch will support this kind of scenario: > > MCFG: > bus r

Re: [RFC PATCH] ACPI/PCI: Fix bus range comparation in pci_mcfg_lookup

2017-01-03 Thread Zhou Wang
On 2017/1/3 14:39, Tomasz Nowicki wrote: > On 22.12.2016 10:07, Zhou Wang wrote: >> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for >> each >> host bridge should be in the coverage of bus range of related PCIe segment. >> >> This patch will support this kind of scenario

Re: [RFC PATCH] ACPI/PCI: Fix bus range comparation in pci_mcfg_lookup

2017-01-02 Thread Tomasz Nowicki
On 22.12.2016 10:07, Zhou Wang wrote: Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each host bridge should be in the coverage of bus range of related PCIe segment. This patch will support this kind of scenario: MCFG: bus range: 0x00~0xff. segment:

Re: [RFC PATCH] ACPI/PCI: Fix bus range comparation in pci_mcfg_lookup

2017-01-02 Thread Zhou Wang
On 2016/12/22 17:07, Zhou Wang wrote: > Multiple PCIe host bridges may exists in one PCIe segment. So bus range for > each > host bridge should be in the coverage of bus range of related PCIe segment. > > This patch will support this kind of scenario: > > MCFG: > bus range: 0x00~0xff. >

[RFC PATCH] ACPI/PCI: Fix bus range comparation in pci_mcfg_lookup

2016-12-22 Thread Zhou Wang
Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each host bridge should be in the coverage of bus range of related PCIe segment. This patch will support this kind of scenario: MCFG: bus range: 0x00~0xff. segment: 0. DSDT: host bridge 1: