On Tue, Nov 06, 2018 at 12:03:17PM +0200, Nick Kossifidis wrote:
> Στις 2018-11-05 21:38, Palmer Dabbelt έγραψε:
> > On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh...@kernel.org wrote:
> > > On Thu, Nov 1, 2018 at 6:04 PM Atish Patra
> > > wrote:
> > > >
> > > > Define a RISC-V cpu topology. This
Στις 2018-11-05 21:38, Palmer Dabbelt έγραψε:
On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh...@kernel.org wrote:
On Thu, Nov 1, 2018 at 6:04 PM Atish Patra
wrote:
Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
But it doesn't need a separate thread node for defining SMT
On 11/5/18 12:11 PM, Rob Herring wrote:
On Mon, Nov 5, 2018 at 1:39 PM Palmer Dabbelt wrote:
On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh...@kernel.org wrote:
On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote:
Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
But it doe
On Mon, Nov 5, 2018 at 1:39 PM Palmer Dabbelt wrote:
>
> On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh...@kernel.org wrote:
> > On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote:
> >>
> >> Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
> >> But it doesn't need a separate thr
On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh...@kernel.org wrote:
On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote:
Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
But it doesn't need a separate thread node for defining SMT systems.
Multiple cpu phandle properties can be
On Fri, Nov 2, 2018 at 3:53 PM Atish Patra wrote:
>
> On 11/2/18 8:50 AM, Sudeep Holla wrote:
> > On Fri, Nov 02, 2018 at 10:11:38AM -0500, Rob Herring wrote:
> >> On Fri, Nov 2, 2018 at 8:31 AM Sudeep Holla wrote:
> >>>
> >>> On Fri, Nov 02, 2018 at 08:09:39AM -0500, Rob Herring wrote:
> On
On 11/2/18 8:50 AM, Sudeep Holla wrote:
On Fri, Nov 02, 2018 at 10:11:38AM -0500, Rob Herring wrote:
On Fri, Nov 2, 2018 at 8:31 AM Sudeep Holla wrote:
On Fri, Nov 02, 2018 at 08:09:39AM -0500, Rob Herring wrote:
On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote:
Define a RISC-V cpu topolo
On 11/2/18 6:09 AM, Rob Herring wrote:
On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote:
Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
But it doesn't need a separate thread node for defining SMT systems.
Multiple cpu phandle properties can be parsed to identify the sibli
On Fri, Nov 02, 2018 at 10:11:38AM -0500, Rob Herring wrote:
> On Fri, Nov 2, 2018 at 8:31 AM Sudeep Holla wrote:
> >
> > On Fri, Nov 02, 2018 at 08:09:39AM -0500, Rob Herring wrote:
> > > On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote:
> > > >
> > > > Define a RISC-V cpu topology. This is base
On Fri, Nov 2, 2018 at 8:31 AM Sudeep Holla wrote:
>
> On Fri, Nov 02, 2018 at 08:09:39AM -0500, Rob Herring wrote:
> > On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote:
> > >
> > > Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
> > > But it doesn't need a separate thread no
On Fri, Nov 02, 2018 at 08:09:39AM -0500, Rob Herring wrote:
> On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote:
> >
> > Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
> > But it doesn't need a separate thread node for defining SMT systems.
> > Multiple cpu phandle properties
On Thu, Nov 1, 2018 at 6:04 PM Atish Patra wrote:
>
> Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
> But it doesn't need a separate thread node for defining SMT systems.
> Multiple cpu phandle properties can be parsed to identify the sibling
> hardware threads. Moreover, we
Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
But it doesn't need a separate thread node for defining SMT systems.
Multiple cpu phandle properties can be parsed to identify the sibling
hardware threads. Moreover, we do not have cluster concept in RISC-V.
So package is a bette
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