Hi Will,
On 7/24/2012 5:08 AM, Will Deacon wrote:
Hi Cyril,
Thanks for this, certainly looks like an interesting platform!
Of course, in order to perform any sort of sensible review, I'll need some
silicon to test it on :)
We have (so far) been testing this on software simulators, and we ha
Hi Cyril,
Thanks for this, certainly looks like an interesting platform!
Of course, in order to perform any sort of sensible review, I'll need some
silicon to test it on :)
On Tue, Jul 24, 2012 at 02:09:02AM +0100, Cyril Chemparathy wrote:
> TI's scalable KeyStone II architecture includes suppor
TI's scalable KeyStone II architecture includes support for both TMS320C66x
floating point DSPs and ARM Cortex-A15 clusters, for a mixture of up to 32
cores per SoC. The solution is optimized around a high performance chip
interconnect and a rich set of on chip peripherals. Please refer [1] for
i
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