Darren Hart wrote:
> On Wed, Oct 26, 2016 at 11:43:24PM +0200, Thomas Gleixner wrote:
> > On Wed, 26 Oct 2016, Darren Hart wrote:
> > > On Mon, Oct 24, 2016 at 01:38:54PM +, Tirdea, Irina wrote:
> > > > intel_pmc_* drivers or is it enough to move it as a standalone
> > > > driver for now?
> > >
On Wed, Oct 26, 2016 at 11:43:24PM +0200, Thomas Gleixner wrote:
> On Wed, 26 Oct 2016, Darren Hart wrote:
> > On Mon, Oct 24, 2016 at 01:38:54PM +, Tirdea, Irina wrote:
> > > intel_pmc_* drivers or is it enough to move it as a standalone driver for
> > > now?
> >
> > If the functionality is
On Wed, 26 Oct 2016, Darren Hart wrote:
> On Mon, Oct 24, 2016 at 01:38:54PM +, Tirdea, Irina wrote:
> > intel_pmc_* drivers or is it enough to move it as a standalone driver for
> > now?
>
> If the functionality is substantially different, then I don't see a
> compelling, and certainly not a
On Mon, Oct 24, 2016 at 01:38:54PM +, Tirdea, Irina wrote:
> > On Thu, Oct 20, 2016 at 11:52:38PM +0200, Thomas Gleixner wrote:
> > > On Mon, 17 Oct 2016, Irina Tirdea wrote:
> > > > The patch has already been reviewed by Stephen Boyd [1].
> > > > The only remaining question is the one pointed
e...@alsa-project.org; Mark Brown; Takashi Iwai; Bossart, Pierre-louis;
> LKML; Pierre-Louis Bossart
> Subject: Re: [RESEND PATCH v4] clk: x86: Add Atom PMC platform clocks
>
> On Thu, Oct 20, 2016 at 11:52:38PM +0200, Thomas Gleixner wrote:
> > On Mon, 17 Oct 2016, Irina Tirdea
On Thu, Oct 20, 2016 at 11:52:38PM +0200, Thomas Gleixner wrote:
> On Mon, 17 Oct 2016, Irina Tirdea wrote:
> > The patch has already been reviewed by Stephen Boyd [1].
> > The only remaining question is the one pointed out by Stephen:
> > "Will there be problems if this merges through clk tree? If
On Mon, 17 Oct 2016, Irina Tirdea wrote:
> The patch has already been reviewed by Stephen Boyd [1].
> The only remaining question is the one pointed out by Stephen:
> "Will there be problems if this merges through clk tree? If so we
> could take the clk driver part and the platform data include par
The BayTrail and CherryTrail platforms provide platform clocks
through their Power Management Controller (PMC).
The SoC supports up to 6 clocks (PMC_PLT_CLK[5:0]) with a
frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail
an a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks
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