Hi Chanwoo
On 14.05.2014 08:57, Chanwoo Choi wrote:
> On 05/14/2014 01:28 AM, Tomasz Figa wrote:
>> On 13.05.2014 13:49, Chanwoo Choi wrote:
>>> On 04/26/2014 09:39 AM, Tomasz Figa wrote:
On 25.04.2014 03:16, Chanwoo Choi wrote:
> +/* GATE_BLOCK */
> +GATE(CLK_BLOCK_LCD, "bloc
Hi Tomasz,
On 05/14/2014 01:28 AM, Tomasz Figa wrote:
> Hi Chanwoo,
>
> On 13.05.2014 13:49, Chanwoo Choi wrote:
>> Hi Tomasz,
>>
>> On 04/26/2014 09:39 AM, Tomasz Figa wrote:
>>> Hi Chanwoo,
>>>
>>> On 25.04.2014 03:16, Chanwoo Choi wrote:
From: Tomasz Figa
This patch add new the
Hi Chanwoo,
On 13.05.2014 13:49, Chanwoo Choi wrote:
> Hi Tomasz,
>
> On 04/26/2014 09:39 AM, Tomasz Figa wrote:
>> Hi Chanwoo,
>>
>> On 25.04.2014 03:16, Chanwoo Choi wrote:
>>> From: Tomasz Figa
>>>
>>> This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
>>> using common c
Hi Tomasz,
On 04/26/2014 09:39 AM, Tomasz Figa wrote:
> Hi Chanwoo,
>
> On 25.04.2014 03:16, Chanwoo Choi wrote:
>> From: Tomasz Figa
>>
>> This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
>> using common clock framework. The CMU (Clock Management Unit) of Exynos3250
>> c
Hi Chanwoo,
On 25.04.2014 03:16, Chanwoo Choi wrote:
From: Tomasz Figa
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common clock framework. The CMU (Clock Management Unit) of Exynos3250
control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses
From: Tomasz Figa
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common clock framework. The CMU (Clock Management Unit) of Exynos3250
control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
and function clocks for individual IPs.
The CMU of Ex
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