On 27/01/17 09:24, Chris Packham wrote:
> On 27/01/17 04:10, Gregory CLEMENT wrote:
>>> + internal-regs {
>
> [snip]
>
>>> +
>>> + dfx-registers {
>> node label
>>
>
> [snip]
>
>>> + switch {
>> node label
>>
>
> These are peers to the internal-regs, i.e. parts of the
On 27/01/17 04:10, Gregory CLEMENT wrote:
>> +internal-regs {
[snip]
>> +
>> +dfx-registers {
> node label
>
[snip]
>> +switch {
> node label
>
These are peers to the internal-regs, i.e. parts of the SoC with
mappable windows in the address space. Do they r
On 27/01/17 04:10, Gregory CLEMENT wrote:
> Hi Chris,
>
> On ven., janv. 06 2017, Chris Packham
> wrote:
>
>> The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
>> with integrated CPUs. They are similar to the Armada XP SoCs but have
>> different I/O interfaces.
>
> Before se
Hi Chris,
On ven., janv. 06 2017, Chris Packham
wrote:
> The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
> with integrated CPUs. They are similar to the Armada XP SoCs but have
> different I/O interfaces.
Before sending a new version I have a few remarks:
> diff --gi
On Fri, Jan 06, 2017 at 05:15:01PM +1300, Chris Packham wrote:
> The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
> with integrated CPUs. They are similar to the Armada XP SoCs but have
> different I/O interfaces.
>
> Signed-off-by: Chris Packham
> ---
> Changes in v2:
>
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham
---
Changes in v2:
- Update devicetree binding documentation to reflect that 98DX3336 and
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