Quoting Boris BREZILLON (2014-09-22 02:04:25)
> On Fri, 19 Sep 2014 14:33:19 +0200
> Nicolas Ferre wrote:
>
> > On 15/09/2014 18:15, Alexandre Belloni :
> > > Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix
> > > interconnect (h32mx) has a clock that can be setup at the hal
On Fri, 19 Sep 2014 14:33:19 +0200
Nicolas Ferre wrote:
> On 15/09/2014 18:15, Alexandre Belloni :
> > Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix
> > interconnect (h32mx) has a clock that can be setup at the half of the h64mx
> > clock (which is mck). The h32mx clock c
Hi Alexandre,
Sorry for the late reply.
On Mon, 15 Sep 2014 18:15:53 +0200
Alexandre Belloni wrote:
> Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix
> interconnect (h32mx) has a clock that can be setup at the half of the h64mx
> clock (which is mck). The h32mx clock can
On 15/09/2014 18:15, Alexandre Belloni :
> Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix
> interconnect (h32mx) has a clock that can be setup at the half of the h64mx
> clock (which is mck). The h32mx clock can not exceed 90 MHz.
>
> Signed-off-by: Alexandre Belloni
Okay
Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix
interconnect (h32mx) has a clock that can be setup at the half of the h64mx
clock (which is mck). The h32mx clock can not exceed 90 MHz.
Signed-off-by: Alexandre Belloni
---
Cc:Mike Turquette
.../devicetree/bindings/clock/a
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