Lorenzo,
On Tue, Feb 5, 2019 at 11:13 PM Lorenzo Pieralisi
wrote:
>
> On Tue, Feb 05, 2019 at 11:09:19AM +0530, Subrahmanya Lingappa wrote:
> > Reviewed-by: Subrahmanya Lingappa
>
> I have a feeling you do not read what I write.
My apologies, I do read. I am new to reviewing process and trying
On Tue, Feb 05, 2019 at 11:09:19AM +0530, Subrahmanya Lingappa wrote:
> Reviewed-by: Subrahmanya Lingappa
I have a feeling you do not read what I write. Please never top-post.
Read this, especially the email etiquette section:
https://kernelnewbies.org/PatchCulture
>
>
>
> On Tue, Jan 29, 2
Reviewed-by: Subrahmanya Lingappa
On Tue, Jan 29, 2019 at 1:38 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> It's confused that R/W some registers by csr_readl()/csr_writel(),
> while others by read_paged_register()/write_paged_register().
> Actually the low 3KB of 4KB PCIe configure space ca
From: Hou Zhiqiang
It's confused that R/W some registers by csr_readl()/csr_writel(),
while others by read_paged_register()/write_paged_register().
Actually the low 3KB of 4KB PCIe configure space can be accessed
directly and high 1KB is paging area. So this patch uniformed the
register accessors
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