Re: [PATCHv3] soc: qcom: llcc: Support chipsets that can write to llcc registers

On 2020-09-09 12:38, Stephen Boyd wrote: Quoting Sai Prakash Ranjan (2020-09-09 00:04:00) Hi, On 2020-09-09 00:02, Stephen Boyd wrote: > Quoting Sai Prakash Ranjan (2020-09-07 22:36:48) >> From: "Isaac J. Manjarres" >> >> Older chipsets may not be allowed to configure certain LLCC registers >>

Re: [PATCHv3] soc: qcom: llcc: Support chipsets that can write to llcc registers

Hi, On 2020-09-08 20:30, Doug Anderson wrote: Hi, On Mon, Sep 7, 2020 at 10:36 PM Sai Prakash Ranjan wrote: --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -73,6 +73,7 @@ struct llcc_edac_reg_data { * @bitmap: Bit map to track the active slice ids * @

Re: [PATCHv3] soc: qcom: llcc: Support chipsets that can write to llcc registers

Hi, On 2020-09-09 00:02, Stephen Boyd wrote: Quoting Sai Prakash Ranjan (2020-09-07 22:36:48) From: "Isaac J. Manjarres" Older chipsets may not be allowed to configure certain LLCC registers as that is handled by the secure side software. However, this is not the case for newer chipsets and t

Re: [PATCHv3] soc: qcom: llcc: Support chipsets that can write to llcc registers

Hi, On Mon, Sep 7, 2020 at 10:36 PM Sai Prakash Ranjan wrote: > > --- a/include/linux/soc/qcom/llcc-qcom.h > +++ b/include/linux/soc/qcom/llcc-qcom.h > @@ -73,6 +73,7 @@ struct llcc_edac_reg_data { > * @bitmap: Bit map to track the active slice ids > * @offsets: Pointer to the bank offsets ar

[PATCHv3] soc: qcom: llcc: Support chipsets that can write to llcc registers

From: "Isaac J. Manjarres" Older chipsets may not be allowed to configure certain LLCC registers as that is handled by the secure side software. However, this is not the case for newer chipsets and they must configure these registers according to the contents of the SCT table, while keeping in mi