> From: Will Deacon [mailto:will.dea...@arm.com]
> Hi Daniel,
>
> On Thu, Nov 16, 2017 at 06:40:46AM +, Daniel Lustig wrote:
> > > > In that case, maybe we should just start out having a fence on
> > > > both sides for
> > >
> > > Actually, given your architecture is RCsc rather than RCpc, so
Hi Daniel,
On Thu, Nov 16, 2017 at 06:40:46AM +, Daniel Lustig wrote:
> > > In that case, maybe we should just start out having a fence on both
> > > sides for
> >
> > Actually, given your architecture is RCsc rather than RCpc, so I think maybe
> > you could follow the way that ARM uses(i.e.
> > In that case, maybe we should just start out having a fence on both
> > sides for
>
> Actually, given your architecture is RCsc rather than RCpc, so I think maybe
> you could follow the way that ARM uses(i.e. relaxed load + release store + a
> full barrier). You can see the commit log of 8e86f
On Wed, 15 Nov 2017 15:59:44 PST (-0800), Daniel Lustig wrote:
On Wed, 15 Nov 2017 10:06:01 PST (-0800), will.dea...@arm.com wrote:
On Tue, Nov 14, 2017 at 12:30:59PM -0800, Palmer Dabbelt wrote:
> On Tue, 24 Oct 2017 07:10:33 PDT (-0700), will.dea...@arm.com wrote:
>>On Tue, Sep 26, 2017 at 06:
> > Bergmann ; Olof Johansson ; linux-
> > ker...@vger.kernel.org; patc...@groups.riscv.org; pet...@infradead.org
> > Subject: Re: [patches] Re: [PATCH v9 05/12] RISC-V: Atomic and Locking Code
> >
> > On Wed, Nov 15, 2017 at 11:59:44PM +, Daniel Lustig wrote
groups.riscv.org; pet...@infradead.org
> Subject: Re: [patches] Re: [PATCH v9 05/12] RISC-V: Atomic and Locking Code
>
> On Wed, Nov 15, 2017 at 11:59:44PM +, Daniel Lustig wrote:
> > > On Wed, 15 Nov 2017 10:06:01 PST (-0800), will.dea...@arm.com wrote:
> > >> On Tue, Nov
On Wed, Nov 15, 2017 at 11:59:44PM +, Daniel Lustig wrote:
> > On Wed, 15 Nov 2017 10:06:01 PST (-0800), will.dea...@arm.com wrote:
> >> On Tue, Nov 14, 2017 at 12:30:59PM -0800, Palmer Dabbelt wrote:
> >> > On Tue, 24 Oct 2017 07:10:33 PDT (-0700), will.dea...@arm.com wrote:
> >> >>On Tue, Sep
> On Wed, 15 Nov 2017 10:06:01 PST (-0800), will.dea...@arm.com wrote:
>> On Tue, Nov 14, 2017 at 12:30:59PM -0800, Palmer Dabbelt wrote:
>> > On Tue, 24 Oct 2017 07:10:33 PDT (-0700), will.dea...@arm.com wrote:
>> >>On Tue, Sep 26, 2017 at 06:56:31PM -0700, Palmer Dabbelt wrote:
> >
> > Hi Palmer,
On Wed, 15 Nov 2017 10:06:01 PST (-0800), will.dea...@arm.com wrote:
Hi Palmer,
On Tue, Nov 14, 2017 at 12:30:59PM -0800, Palmer Dabbelt wrote:
On Tue, 24 Oct 2017 07:10:33 PDT (-0700), will.dea...@arm.com wrote:
>On Tue, Sep 26, 2017 at 06:56:31PM -0700, Palmer Dabbelt wrote:
>>+ATOMIC_OPS(add
Hi Palmer,
On Tue, Nov 14, 2017 at 12:30:59PM -0800, Palmer Dabbelt wrote:
> On Tue, 24 Oct 2017 07:10:33 PDT (-0700), will.dea...@arm.com wrote:
> >On Tue, Sep 26, 2017 at 06:56:31PM -0700, Palmer Dabbelt wrote:
> >>+ATOMIC_OPS(add, add, +, i)
> >>+ATOMIC_OPS(sub, add, +, -i)
> >>+ATOMIC_OPS(and
On Tue, 24 Oct 2017 07:10:33 PDT (-0700), will.dea...@arm.com wrote:
Hi Palmer,
Some late comments on this which you might want to address as you get the
chance.
Sorry, this disappeared into my inbox. I've replied in-line to all your
comments, but in the interest of making sure I didn't lose
Hi Palmer,
Some late comments on this which you might want to address as you get the
chance.
On Tue, Sep 26, 2017 at 06:56:31PM -0700, Palmer Dabbelt wrote:
> This contains all the code that directly interfaces with the RISC-V
> memory model. While this code corforms to the current RISC-V ISA
>
This contains all the code that directly interfaces with the RISC-V
memory model. While this code corforms to the current RISC-V ISA
specifications (user 2.2 and priv 1.10), the memory model is somewhat
underspecified in those documents. There is a working group that hopes
to produce a formal mem
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