On Thu, Oct 13, 2016 at 03:25:42PM -0400, Rich Felker wrote:
> On Wed, Oct 12, 2016 at 11:31:26PM +0200, Daniel Lezcano wrote:
> > > > --> System Type
> > > >
> > > > That is what you are looking for, a SUPERH config option selecting all
> > > > the
> > > > common options and then a JCORE config
On Wed, Oct 12, 2016 at 11:31:26PM +0200, Daniel Lezcano wrote:
> > > --> System Type
> > >
> > > That is what you are looking for, a SUPERH config option selecting all the
> > > common options and then a JCORE config option adding the different missing
> > > bits, namely the CLKSRC_JCORE_PIT.
> >
On Wed, Oct 12, 2016 at 11:31:26PM +0200, Daniel Lezcano wrote:
> > > I understand the goal is to have one single configuration and everything
> > > DT based and it sounds great but what is missing here is just a subarch,
> > > not an option to enable/disable the timer.
> > >
> > > Give a try with
On Wed, Oct 12, 2016 at 01:02:36PM -0400, Rich Felker wrote:
> On Wed, Oct 12, 2016 at 11:27:11AM +0200, Daniel Lezcano wrote:
> > > > Are the CPUs on always-on power down ?
> > >
> > > For now they are always on and don't even have the sleep instruction
> > > (i.e. stop cpu clock until interrupt)
On Wed, Oct 12, 2016 at 11:27:11AM +0200, Daniel Lezcano wrote:
> > > Are the CPUs on always-on power down ?
> >
> > For now they are always on and don't even have the sleep instruction
> > (i.e. stop cpu clock until interrupt) implemented. Adding sleep will
> > be the first power-saving step, and
On Tue, Oct 11, 2016 at 04:28:50PM -0400, Rich Felker wrote:
> On Tue, Oct 11, 2016 at 08:18:12PM +0200, Daniel Lezcano wrote:
> >
> > Hi Rich,
> >
> > On Sun, Oct 09, 2016 at 05:34:22AM +, Rich Felker wrote:
> > > At the hardware level, the J-Core PIT is integrated with the interrupt
> > > c
On Tue, Oct 11, 2016 at 08:18:12PM +0200, Daniel Lezcano wrote:
>
> Hi Rich,
>
> On Sun, Oct 09, 2016 at 05:34:22AM +, Rich Felker wrote:
> > At the hardware level, the J-Core PIT is integrated with the interrupt
> > controller, but it is represented as its own device and has an
> > independe
Hi Rich,
On Sun, Oct 09, 2016 at 05:34:22AM +, Rich Felker wrote:
> At the hardware level, the J-Core PIT is integrated with the interrupt
> controller, but it is represented as its own device and has an
> independent programming interface. It provides a 12-bit countdown
> timer, which is not
At the hardware level, the J-Core PIT is integrated with the interrupt
controller, but it is represented as its own device and has an
independent programming interface. It provides a 12-bit countdown
timer, which is not presently used, and a periodic timer. The interval
length for the latter is pro
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