Hi Vinod,
On Tue, Mar 17, 2015 at 3:49 PM, Vinod Koul wrote:
> On Tue, Mar 17, 2015 at 03:03:14PM +0530, Rameshwar Sahu wrote:
>> Hi Vinod,
>>
>> On Mon, Mar 16, 2015 at 11:01 PM, Rameshwar Sahu wrote:
>> > Hi Vinod,
>> >
>> > On Mon, Mar 16, 2015 at 9:56 PM, Vinod Koul wrote:
>> >> On Mon, Mar
On Tue, Mar 17, 2015 at 03:03:14PM +0530, Rameshwar Sahu wrote:
> Hi Vinod,
>
> On Mon, Mar 16, 2015 at 11:01 PM, Rameshwar Sahu wrote:
> > Hi Vinod,
> >
> > On Mon, Mar 16, 2015 at 9:56 PM, Vinod Koul wrote:
> >> On Mon, Mar 16, 2015 at 05:24:34PM +0530, Rameshwar Sahu wrote:
> >>> >> >> +stati
Hi Vinod,
On Mon, Mar 16, 2015 at 11:01 PM, Rameshwar Sahu wrote:
> Hi Vinod,
>
> On Mon, Mar 16, 2015 at 9:56 PM, Vinod Koul wrote:
>> On Mon, Mar 16, 2015 at 05:24:34PM +0530, Rameshwar Sahu wrote:
>>> >> >> +static void xgene_dma_free_desc_list_reverse(struct xgene_dma_chan
>>> >> >> *chan,
Hi Vinod,
On Mon, Mar 16, 2015 at 9:56 PM, Vinod Koul wrote:
> On Mon, Mar 16, 2015 at 05:24:34PM +0530, Rameshwar Sahu wrote:
>> >> >> +static void xgene_dma_free_desc_list_reverse(struct xgene_dma_chan
>> >> >> *chan,
>> >> >> + struct list_head *list)
On Mon, Mar 16, 2015 at 05:24:34PM +0530, Rameshwar Sahu wrote:
> >> >> +static void xgene_dma_free_desc_list_reverse(struct xgene_dma_chan
> >> >> *chan,
> >> >> + struct list_head *list)
> >> > do we really care about free order?
> >>
> >> Yes it start de
Hi Vinod,
On Mon, Mar 16, 2015 at 4:57 PM, Vinod Koul wrote:
> On Mon, Mar 16, 2015 at 04:00:22PM +0530, Rameshwar Sahu wrote:
>
>> >> +static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor(
>> >> + struct xgene_dma_chan *chan)
>> >> +{
>> >> + struct xgene
On Mon, Mar 16, 2015 at 04:00:22PM +0530, Rameshwar Sahu wrote:
> >> +static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor(
> >> + struct xgene_dma_chan *chan)
> >> +{
> >> + struct xgene_dma_desc_sw *desc;
> >> + dma_addr_t phys;
> >> +
> >> + desc
Hi Vinod,
On Mon, Mar 16, 2015 at 2:57 PM, Vinod Koul wrote:
> On Thu, Mar 12, 2015 at 04:45:19PM +0530, Rameshwar Prasad Sahu wrote:
>> +/* DMA ring csr registers and bit definations */
>> +#define DMA_RING_CONFIG 0x04
>> +#define DMA_RING_ENABLE BIT(31)
Hi Vinod,
On Mon, Mar 16, 2015 at 2:57 PM, Vinod Koul wrote:
> On Thu, Mar 12, 2015 at 04:45:19PM +0530, Rameshwar Prasad Sahu wrote:
>> +/* DMA ring csr registers and bit definations */
>> +#define DMA_RING_CONFIG 0x04
>> +#define DMA_RING_ENABLE BIT(31
On Thu, Mar 12, 2015 at 04:45:19PM +0530, Rameshwar Prasad Sahu wrote:
> +/* DMA ring csr registers and bit definations */
> +#define DMA_RING_CONFIG 0x04
> +#define DMA_RING_ENABLE BIT(31)
> +#define DMA_RING_ID 0x08
> +#define DMA_RING_ID
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene
SoC DMA engine consists of 4 DMA channels for performing DMA operations.
These DMA operations include memory copy, scatter-gather memory copy,
raid5 xor, and raid6 p+q offloading.
Signed-off-by: Rameshwar Prasad Sahu
Signe
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