Hi Anup,
On Mon, Jun 1, 2020 at 12:09 PM Anup Patel wrote:
>
> On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote:
> >
> > On 2020-05-31 11:06, Anup Patel wrote:
> > > On Sun, May 31, 2020 at 3:03 PM Marc Zyngier wrote:
> > >>
> > >> On 2020-05-31 06:36, Anup Patel wrote:
> > >> > On Sat, May 3
On Mon, Jun 1, 2020 at 1:11 PM Marc Zyngier wrote:
>
> On 2020-06-01 05:09, Anup Patel wrote:
> > On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote:
> >>
> >> On 2020-05-31 11:06, Anup Patel wrote:
>
> [...]
>
> > Also, the PLIC spec is now owned by RISC-V foundation (not SiFive) so
> > we will
On 2020-06-01 05:09, Anup Patel wrote:
On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote:
On 2020-05-31 11:06, Anup Patel wrote:
[...]
Also, the PLIC spec is now owned by RISC-V foundation (not SiFive) so
we will have to rename the driver to "irq-riscv-plic" and will have a
new
generic c
On Sun, May 31, 2020 at 4:23 PM Marc Zyngier wrote:
>
> On 2020-05-31 11:06, Anup Patel wrote:
> > On Sun, May 31, 2020 at 3:03 PM Marc Zyngier wrote:
> >>
> >> On 2020-05-31 06:36, Anup Patel wrote:
> >> > On Sat, May 30, 2020 at 5:31 PM Marc Zyngier wrote:
> >>
> >> [...]
> >>
> >> >> >
On 2020-05-31 11:06, Anup Patel wrote:
On Sun, May 31, 2020 at 3:03 PM Marc Zyngier wrote:
On 2020-05-31 06:36, Anup Patel wrote:
> On Sat, May 30, 2020 at 5:31 PM Marc Zyngier wrote:
[...]
>> > plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
>>
>> Why do you need to both disable
On Sun, May 31, 2020 at 3:03 PM Marc Zyngier wrote:
>
> On 2020-05-31 06:36, Anup Patel wrote:
> > On Sat, May 30, 2020 at 5:31 PM Marc Zyngier wrote:
>
> [...]
>
> >> > plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
> >>
> >> Why do you need to both disable the interrupt *and* change
On 2020-05-31 06:36, Anup Patel wrote:
On Sat, May 30, 2020 at 5:31 PM Marc Zyngier wrote:
[...]
> plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
Why do you need to both disable the interrupt *and* change the
priority
threshold? It seems to be that one of them should be enough
On Sat, May 30, 2020 at 5:31 PM Marc Zyngier wrote:
>
> On 2020-05-30 11:07, Anup Patel wrote:
> > The RISC-V per-HART local interrupt controller manages software
> > interrupts, timer interrupts, external interrupts (which are routed
> > via the platform level interrupt controller) and other per-
On 2020-05-30 11:07, Anup Patel wrote:
The RISC-V per-HART local interrupt controller manages software
interrupts, timer interrupts, external interrupts (which are routed
via the platform level interrupt controller) and other per-HART
local interrupts.
This patch adds a driver for the RISC-V loc
The RISC-V per-HART local interrupt controller manages software
interrupts, timer interrupts, external interrupts (which are routed
via the platform level interrupt controller) and other per-HART
local interrupts.
This patch adds a driver for the RISC-V local interrupt controller.
It is a major re
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