On 06/14/2016 04:59 PM, Benjamin Herrenschmidt wrote:
> On Tue, 2016-06-14 at 16:17 +0530, Shreyas B Prabhu wrote:
>
>>
>> I ignored adding this check because this is part of initcall and we are
>> unlikely to run out of memory at this state. But I'll add the check in
>> next version.
>
> Why d
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On Tue, 2016-06-14 at 16:17 +0530, Shreyas B Prabhu wrote:
>
> I ignored adding this check because this is part of initcall and we are
> unlikely to run out of memory at this state. But I'll add the check in
> next version.
Why do you malloc the u64 array and not the string pointer array ?
Shoul
On 06/14/2016 03:18 AM, Benjamin Herrenschmidt wrote:
> On Wed, 2016-06-08 at 11:54 -0500, Shreyas B. Prabhu wrote:
>>
>> /*
>> * States for dedicated partition case.
>> */
>> @@ -167,6 +183,8 @@ static int powernv_add_idle_states(void)
>> int nr_idle_states = 1; /* Snooze */
>> in
On 06/13/2016 09:04 PM, Daniel Lezcano wrote:
> On Wed, Jun 08, 2016 at 11:54:30AM -0500, Shreyas B. Prabhu wrote:
>> POWER ISA v3 defines a new idle processor core mechanism. In summary,
>> a) new instruction named stop is added.
>> b) new per thread SPR named PSSCR is added which controls the
On Wed, 2016-06-08 at 11:54 -0500, Shreyas B. Prabhu wrote:
>
> /*
> * States for dedicated partition case.
> */
> @@ -167,6 +183,8 @@ static int powernv_add_idle_states(void)
> int nr_idle_states = 1; /* Snooze */
> int dt_idle_states;
> u32 *latency_ns, *residency_ns, *fla
On Wed, Jun 08, 2016 at 11:54:30AM -0500, Shreyas B. Prabhu wrote:
> POWER ISA v3 defines a new idle processor core mechanism. In summary,
> a) new instruction named stop is added.
> b) new per thread SPR named PSSCR is added which controls the behavior
> of stop instruction.
>
> Supported
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
Supported idle states and value to be written to PSSCR register to enter
any idle stat
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