Re: [PATCH v6 1/3] PCI: altera: Add Stratix 10 PCIe support

2019-03-03 Thread Ley Foon Tan
On Fri, 2019-03-01 at 14:15 +, Lorenzo Pieralisi wrote: > On Fri, Mar 01, 2019 at 08:50:48AM +0800, Ley Foon Tan wrote: > > > > On Thu, 2019-02-28 at 10:56 +, Lorenzo Pieralisi wrote: > > > > > > On Thu, Feb 28, 2019 at 06:52:50PM +0800, Ley Foon Tan wrote: > > > > > > [...] > > > > > >

Re: [PATCH v6 1/3] PCI: altera: Add Stratix 10 PCIe support

2019-03-01 Thread Lorenzo Pieralisi
On Fri, Mar 01, 2019 at 08:50:48AM +0800, Ley Foon Tan wrote: > On Thu, 2019-02-28 at 10:56 +, Lorenzo Pieralisi wrote: > > On Thu, Feb 28, 2019 at 06:52:50PM +0800, Ley Foon Tan wrote: > > > > [...] > > > > > > > > +static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 > > > *value)

Re: [PATCH v6 1/3] PCI: altera: Add Stratix 10 PCIe support

2019-02-28 Thread Ley Foon Tan
On Thu, 2019-02-28 at 10:56 +, Lorenzo Pieralisi wrote: > On Thu, Feb 28, 2019 at 06:52:50PM +0800, Ley Foon Tan wrote: > > [...] > > > > > +static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 > > *value) > > +{ > > + int i; > > + u32 ctrl; > > + u32 comp_status; > > + u32 d

Re: [PATCH v6 1/3] PCI: altera: Add Stratix 10 PCIe support

2019-02-28 Thread Lorenzo Pieralisi
On Thu, Feb 28, 2019 at 06:52:50PM +0800, Ley Foon Tan wrote: [...] > +static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value) > +{ > + int i; > + u32 ctrl; > + u32 comp_status; > + u32 dw[4]; > + u32 count; > + > + for (i = 0; i < TLP_LOOP; i++) { > +

[PATCH v6 1/3] PCI: altera: Add Stratix 10 PCIe support

2019-02-27 Thread Ley Foon Tan
Add PCIe Root Port support for Stratix 10 device. Main differences compare with PCIe Root Port IP on Cyclone V and Arria 10 devices: - HIP interface to access Root Port configuration register. - TLP programming flow: - One REG0 register - Don't need to check alignment Signed-off-by: Ley Foon