Re: [PATCH v5 1/2] i2c: cadence: Handle > 252 byte transfers

2015-01-13 Thread Harini Katakam
Hi, On Tue, Jan 13, 2015 at 4:58 PM, Wolfram Sang wrote: > On Fri, Dec 12, 2014 at 09:48:26AM +0530, Harini Katakam wrote: >> The I2C controller sends a NACK to the slave when transfer size register >> reaches zero, irrespective of the hold bit. So, in order to handle transfers >> greater than 25

Re: [PATCH v5 1/2] i2c: cadence: Handle > 252 byte transfers

2015-01-13 Thread Wolfram Sang
On Fri, Dec 12, 2014 at 09:48:26AM +0530, Harini Katakam wrote: > The I2C controller sends a NACK to the slave when transfer size register > reaches zero, irrespective of the hold bit. So, in order to handle transfers > greater than 252 bytes, the transfer size register has to be maintained at a >

[PATCH v5 1/2] i2c: cadence: Handle > 252 byte transfers

2014-12-11 Thread Harini Katakam
The I2C controller sends a NACK to the slave when transfer size register reaches zero, irrespective of the hold bit. So, in order to handle transfers greater than 252 bytes, the transfer size register has to be maintained at a value >= 1. This patch implements the same. The interrupt status is clea