On Thu, 8 Jun 2017 17:44:19 +0300
Andy Shevchenko andy.shevche...@gmail.com wrote:
>On Thu, Jun 8, 2017 at 5:15 PM, Anatolij Gustschin wrote:
>> On Thu, 8 Jun 2017 02:38:55 +0300
>> Andy Shevchenko andy.shevche...@gmail.com wrote:
>>>On Thu, Jun 8, 2017 at 2:09 AM, Anatolij Gustschin wrote:
On Thu, Jun 8, 2017 at 5:15 PM, Anatolij Gustschin wrote:
> On Thu, 8 Jun 2017 02:38:55 +0300
> Andy Shevchenko andy.shevche...@gmail.com wrote:
>>On Thu, Jun 8, 2017 at 2:09 AM, Anatolij Gustschin wrote:
>>> On Fri, 2 Jun 2017 20:43:21 +0300
>>> Andy Shevchenko andy.shevche...@gmail.com wrote:
On Thu, 8 Jun 2017 02:38:55 +0300
Andy Shevchenko andy.shevche...@gmail.com wrote:
>On Thu, Jun 8, 2017 at 2:09 AM, Anatolij Gustschin wrote:
>> On Fri, 2 Jun 2017 20:43:21 +0300
>> Andy Shevchenko andy.shevche...@gmail.com wrote:
>
>Besides below comments, please, do
>
>s/VSEC_/VSE_/g
>
>for e
On Sun, May 14, 2017 at 10:01 PM, kbuild test robot wrote:
> Hi Anatolij,
>
> [auto build test ERROR on linus/master]
> [also build test ERROR on v4.12-rc1 next-20170512]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
>
> url:
> https://
On Thu, Jun 8, 2017 at 2:09 AM, Anatolij Gustschin wrote:
> On Fri, 2 Jun 2017 20:43:21 +0300
> Andy Shevchenko andy.shevche...@gmail.com wrote:
Besides below comments, please, do
s/VSEC_/VSE_/g
for entire file.
We are following PCI and Thunderbolt pattern for use of Vendor
Specific Extended C
On Fri, 2 Jun 2017 20:43:21 +0300
Andy Shevchenko andy.shevche...@gmail.com wrote:
...
>
>> + void(*write_data)(struct altera_cvp_conf *conf,
>> + u32 val);
>
>Is it too far beyond 80 characters? I would leave it in one line (~83
On Fri, Jun 2, 2017 at 8:43 PM, Andy Shevchenko
wrote:
> On Sun, May 14, 2017 at 6:51 PM, Anatolij Gustschin wrote:
>> Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V
>> and Arria-10 FPGAs via CvP.
>
> Few comments from me.
After addressing them, FWIW,
Reviewed-by: Andy Shevchenk
On Sun, May 14, 2017 at 6:51 PM, Anatolij Gustschin wrote:
> Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V
> and Arria-10 FPGAs via CvP.
Few comments from me.
> +struct altera_cvp_conf {
> + struct fpga_manager *mgr;
> + struct pci_dev *pci_dev;
> +
Hi Alan,
On Sun, 14 May 2017 17:51:22 +0200
Anatolij Gustschin ag...@denx.de wrote:
>Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V
>and Arria-10 FPGAs via CvP.
any comments to this patch? I'll rebase to apply on top of Altera
PS-SPI driver series, so that it can be queued for m
Hi Anatolij,
[auto build test ERROR on linus/master]
[also build test ERROR on v4.12-rc1 next-20170512]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Anatolij-Gustschin/fpga-manager-Add-Altera-
Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V
and Arria-10 FPGAs via CvP.
Signed-off-by: Anatolij Gustschin
---
For building this patch requires https://lkml.org/lkml/2017/5/14/73
Changes in v5:
- use absolute register offset values
- move register bit macros below offset
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