On Wed, Jan 08, 2014 at 05:54:28PM -0800, Stephen Boyd wrote:
> Ok. Borislav, should I resend to add krait_ before these functions?
Yes please - I can't even build-test here so I'm relying on you.
That's why I thought it might be a better idea for this purely arm patch
to go through some other tr
On 01/08/14 16:53, Courtney Cavin wrote:
> On Mon, Dec 30, 2013 at 09:14:14PM +0100, Stephen Boyd wrote:
>> Krait CPUs have a handful of L2 cache controller registers that
>> live behind a cp15 based indirection register. First you program
>> the indirection register (l2cpselr) to point the L2 'win
On Mon, Dec 30, 2013 at 09:14:14PM +0100, Stephen Boyd wrote:
> Krait CPUs have a handful of L2 cache controller registers that
> live behind a cp15 based indirection register. First you program
> the indirection register (l2cpselr) to point the L2 'window'
> register (l2cpdr) at what you want to r
On 01/07/14 15:07, Borislav Petkov wrote:
> On Mon, Dec 30, 2013 at 12:14:14PM -0800, Stephen Boyd wrote:
>> Krait CPUs have a handful of L2 cache controller registers that
>> live behind a cp15 based indirection register. First you program
>> the indirection register (l2cpselr) to point the L2 'wi
On Mon, Dec 30, 2013 at 12:14:14PM -0800, Stephen Boyd wrote:
> Krait CPUs have a handful of L2 cache controller registers that
> live behind a cp15 based indirection register. First you program
> the indirection register (l2cpselr) to point the L2 'window'
> register (l2cpdr) at what you want to r
Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' register to do what you w
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