On Mon, Mar 12, 2018 at 02:36:48PM -0700, matthew.gerl...@linux.intel.com wrote:
>
>
> On Mon, 12 Mar 2018, Wu Hao wrote:
>
> Hi Hao,
>
> Please see my two comments inline.
>
> Thanks,
> Matthew Gerlach
>
> >On Sun, Mar 11, 2018 at 01:09:31PM -0700, matthew.gerl...@linux.intel.com
> >wrote:
On Mon, 12 Mar 2018, Wu Hao wrote:
Hi Hao,
Please see my two comments inline.
Thanks,
Matthew Gerlach
On Sun, Mar 11, 2018 at 01:09:31PM -0700, matthew.gerl...@linux.intel.com wrote:
On Mon, 5 Mar 2018, Alan Tull wrote:
Hi Hao,
I do think we should consider different hw implementation
On Sun, Mar 11, 2018 at 11:29 PM, Wu Hao wrote:
> On Sun, Mar 11, 2018 at 01:09:31PM -0700, matthew.gerl...@linux.intel.com
> wrote:
>>
>> Hi Hao,
>>
>> I do think we should consider different hw implementations with this code
>> because it does look like most of it is generic. Specifically, I
On Sun, Mar 11, 2018 at 01:09:31PM -0700, matthew.gerl...@linux.intel.com wrote:
>
>
> On Mon, 5 Mar 2018, Alan Tull wrote:
>
>
> Hi Hao,
>
> I do think we should consider different hw implementations with this code
> because it does look like most of it is generic. Specifically, I think
> we
On Mon, 5 Mar 2018, Alan Tull wrote:
Hi Hao,
I do think we should consider different hw implementations with this code
because it does look like most of it is generic. Specifically, I think
we should consider DFH based fpga images that have been shipped already,
and I think we need to consid
On Tue, Mar 06, 2018 at 12:29:35PM -0600, Alan Tull wrote:
> On Mon, Mar 5, 2018 at 8:08 PM, Wu Hao wrote:
> > On Mon, Mar 05, 2018 at 04:46:02PM -0600, Alan Tull wrote:
> >> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
> >>
> >> Hi Hao,
> >
> > Hi Alan,
> >
> > Thanks for the comments.
> >
>
On Mon, Mar 5, 2018 at 8:08 PM, Wu Hao wrote:
> On Mon, Mar 05, 2018 at 04:46:02PM -0600, Alan Tull wrote:
>> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
>>
>> Hi Hao,
>
> Hi Alan,
>
> Thanks for the comments.
>
>>
>> We are going to want to be able use different FPGA managers with this
>> f
On Mon, Mar 05, 2018 at 04:46:02PM -0600, Alan Tull wrote:
> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
>
> Hi Hao,
Hi Alan,
Thanks for the comments.
>
> We are going to want to be able use different FPGA managers with this
> framework. The different manager may be part of a different FM
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
We are going to want to be able use different FPGA managers with this
framework. The different manager may be part of a different FME in
fabric or it may be a hardware FPGA manager. Fortunately, at this
point now the changes, noted below,
From: Kang Luwei
Partial Reconfiguration (PR) is the most important function for FME. It
allows reconfiguration for given Port/Accelerated Function Unit (AFU).
It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges,
and invokes fpga-region's interface (fpga_region_program_fpga)
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