Re: [PATCH v4 1/3] iio: adc: vf610: use ADC clock within specification

2015-03-28 Thread Jonathan Cameron
On 24/03/15 12:47, Stefan Agner wrote: > Depending on conversion mode used, the ADC clock (ADCK) needs > to be below a maximum frequency. According to Vybrid's data > sheet this is 20MHz for the low power conversion mode. > > The ADC clock is depending on input clock, which is the bus > clock by d

[PATCH v4 1/3] iio: adc: vf610: use ADC clock within specification

2015-03-24 Thread Stefan Agner
Depending on conversion mode used, the ADC clock (ADCK) needs to be below a maximum frequency. According to Vybrid's data sheet this is 20MHz for the low power conversion mode. The ADC clock is depending on input clock, which is the bus clock by default. Vybrid SoC are typically clocked at at 400M