On Wed, Apr 04, 2018 at 03:06:57PM -0500, Alan Tull wrote:
> On Mon, Apr 2, 2018 at 8:36 PM, Wu Hao wrote:
> > On Mon, Apr 02, 2018 at 02:06:56PM -0500, Alan Tull wrote:
> >> On Sun, Apr 1, 2018 at 11:22 PM, Wu Hao wrote:
> >> > On Thu, Mar 29, 2018 at 04:57:22PM -0500, Alan Tull wrote:
> >> >> O
On Mon, Apr 2, 2018 at 8:36 PM, Wu Hao wrote:
> On Mon, Apr 02, 2018 at 02:06:56PM -0500, Alan Tull wrote:
>> On Sun, Apr 1, 2018 at 11:22 PM, Wu Hao wrote:
>> > On Thu, Mar 29, 2018 at 04:57:22PM -0500, Alan Tull wrote:
>> >> On Mon, Mar 26, 2018 at 9:35 PM, Wu Hao wrote:
>> >>
>> >> Hi Hao,
>>
On Mon, Apr 02, 2018 at 02:06:56PM -0500, Alan Tull wrote:
> On Sun, Apr 1, 2018 at 11:22 PM, Wu Hao wrote:
> > On Thu, Mar 29, 2018 at 04:57:22PM -0500, Alan Tull wrote:
> >> On Mon, Mar 26, 2018 at 9:35 PM, Wu Hao wrote:
> >>
> >> Hi Hao,
> >>
> >> Currently there is one set of functions that h
On Sun, Apr 1, 2018 at 11:22 PM, Wu Hao wrote:
> On Thu, Mar 29, 2018 at 04:57:22PM -0500, Alan Tull wrote:
>> On Mon, Mar 26, 2018 at 9:35 PM, Wu Hao wrote:
>>
>> Hi Hao,
>>
>> Currently there is one set of functions that handles port enable,
>> disable, and reset and it's in dfl.c and dfl.h, so
On Thu, Mar 29, 2018 at 04:57:22PM -0500, Alan Tull wrote:
> On Mon, Mar 26, 2018 at 9:35 PM, Wu Hao wrote:
>
> Hi Hao,
>
> Currently there is one set of functions that handles port enable,
> disable, and reset and it's in dfl.c and dfl.h, so that's not in any
> driver module that can be switche
On Mon, Mar 26, 2018 at 9:35 PM, Wu Hao wrote:
Hi Hao,
Currently there is one set of functions that handles port enable,
disable, and reset and it's in dfl.c and dfl.h, so that's not in any
driver module that can be switched out if necessary for a different
implementation of the port. Finding a
On Mon, Mar 26, 2018 at 12:21:23PM -0500, Alan Tull wrote:
> On Thu, Mar 22, 2018 at 11:33 PM, Wu Hao wrote:
>
> >> > +
> >> > +/*
> >> > + * This function resets the FPGA Port and its accelerator (AFU) by
> >> > function
> >> > + * __fpga_port_disable and __fpga_port_enable (set port soft reset
On Thu, Mar 22, 2018 at 11:33 PM, Wu Hao wrote:
>> > +
>> > +/*
>> > + * This function resets the FPGA Port and its accelerator (AFU) by
>> > function
>> > + * __fpga_port_disable and __fpga_port_enable (set port soft reset bit and
>> > + * then clear it). Userspace can do Port reset at any time
On Thu, Mar 22, 2018 at 04:31:05PM -0500, Alan Tull wrote:
> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
>
> Hi Hao,
Hi Alan
Thanks a lot for the code review and the comments. : )
>
> > Device Feature List (DFL) defines a feature list structure that creates
> > a link list of feature heade
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
> Device Feature List (DFL) defines a feature list structure that creates
> a link list of feature headers within the MMIO space to provide an
> extensible way of adding features. This patch introduces a kernel module
> to provide basic infr
On Wed, Mar 21, 2018 at 06:54:58PM -0500, Alan Tull wrote:
> On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
>
> Hi Hao,
>
> > +static int
> > +build_info_create_dev(struct build_feature_devs_info *binfo,
> > + enum fpga_id_type type, const char *name,
> > +
On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao wrote:
Hi Hao,
> +static int
> +build_info_create_dev(struct build_feature_devs_info *binfo,
> + enum fpga_id_type type, const char *name,
> + void __iomem *ioaddr)
> +{
> + struct platform_device *fdev;
> +
Device Feature List (DFL) defines a feature list structure that creates
a link list of feature headers within the MMIO space to provide an
extensible way of adding features. This patch introduces a kernel module
to provide basic infrastructure to support FPGA devices which implement
the Device Feat
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