From: Andrew Lunn
Date: Sep/06/2019, 15:24:46 (UTC+00:00)
> On Fri, Sep 06, 2019 at 01:31:14PM +, Jose Abreu wrote:
> > From: Voon Weifeng
> > Date: Sep/05/2019, 13:05:30 (UTC+00:00)
> >
> > > DW EQoS v5.xx controllers added capability for interrupt generation
> > > when MDIO interface is d
On Fri, Sep 06, 2019 at 01:31:14PM +, Jose Abreu wrote:
> From: Voon Weifeng
> Date: Sep/05/2019, 13:05:30 (UTC+00:00)
>
> > DW EQoS v5.xx controllers added capability for interrupt generation
> > when MDIO interface is done (GMII Busy bit is cleared).
> > This patch adds support for this int
From: Voon Weifeng
Date: Sep/05/2019, 13:05:30 (UTC+00:00)
> DW EQoS v5.xx controllers added capability for interrupt generation
> when MDIO interface is done (GMII Busy bit is cleared).
> This patch adds support for this interrupt on supported HW to avoid
> polling on GMII Busy bit.
Better leav
From: "Chuah, Kim Tatt"
DW EQoS v5.xx controllers added capability for interrupt generation
when MDIO interface is done (GMII Busy bit is cleared).
This patch adds support for this interrupt on supported HW to avoid
polling on GMII Busy bit.
stmmac_mdio_read() & stmmac_mdio_write() will sleep un
4 matches
Mail list logo
