Re: [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU

2017-05-18 Thread Chen-Yu Tsai
On Thu, May 18, 2017 at 3:39 PM, Maxime Ripard wrote: > On Thu, May 18, 2017 at 11:58:06AM +0800, Chen-Yu Tsai wrote: >> +/* >> + * MMC2 supports both old and new timing modes. When the new timing >> + * mode is active, the output clock rate is halved by two. Here we >> + * treat it as a variable

Re: [PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU

2017-05-18 Thread Maxime Ripard
On Thu, May 18, 2017 at 11:58:06AM +0800, Chen-Yu Tsai wrote: > +/* > + * MMC2 supports both old and new timing modes. When the new timing > + * mode is active, the output clock rate is halved by two. Here we > + * treat it as a variable pre-divider. Note that the pre-divider is > + * _not_ include

[PATCH v3 3/6] clk: sunxi-ng: Add driver for A83T CCU

2017-05-17 Thread Chen-Yu Tsai
The A83T clock control unit is a hybrid of some new style clock designs from the A80, and old style layout from the other Allwinner SoCs. Like the A80, the SoC does not have a low speed 32.768 kHz oscillator. Unlike the A80, there is no clock input either. The only low speed clock available is the