Re: [PATCH v3 3/5] clk: ralink: add clock driver for mt7621 SoC

Hi, On Thu, Nov 19, 2020 at 10:32 AM Chuanhong Guo wrote: > > Hi! > > On Fri, Nov 13, 2020 at 11:46 PM Sergio Paracuellos > wrote: > > [...] > > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile > > new file mode 100644 > > index ..cf6f9216379d > > --- /dev/null

Re: [PATCH v3 3/5] clk: ralink: add clock driver for mt7621 SoC

Hi! On Fri, Nov 13, 2020 at 11:46 PM Sergio Paracuellos wrote: > [...] > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile > new file mode 100644 > index ..cf6f9216379d > --- /dev/null > +++ b/drivers/clk/ralink/Makefile Why ralink? The clock design of mt7621 doe

[PATCH v3 3/5] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or s