On Wed, 2018-07-18 at 10:49 +0100, Lorenzo Pieralisi wrote:
> On Wed, Jul 18, 2018 at 02:02:41PM +0800, Honghui Zhang wrote:
>
>
>
> > > > +static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
> > > > +{
> > > > + struct mtk_pcie *pcie = dev_get_drvdata(dev);
> > > > +
On Wed, Jul 18, 2018 at 02:02:41PM +0800, Honghui Zhang wrote:
> > > +static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
> > > +{
> > > + struct mtk_pcie *pcie = dev_get_drvdata(dev);
> > > + const struct mtk_pcie_soc *soc = pcie->soc;
> > > + struct mtk_pcie_port *port, *tmp;
>
On Tue, 2018-07-17 at 18:15 +0100, Lorenzo Pieralisi wrote:
> [+Rafael, Kevin, Ulf]
>
> On Mon, Jul 02, 2018 at 03:57:43PM +0800, honghui.zh...@mediatek.com wrote:
> > From: Honghui Zhang
> >
> > The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when system
> > suspend, and all the inter
[+Rafael, Kevin, Ulf]
On Mon, Jul 02, 2018 at 03:57:43PM +0800, honghui.zh...@mediatek.com wrote:
> From: Honghui Zhang
>
> The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when system
> suspend, and all the internal control register will be reset after system
> resume. The PCIe link sh
From: Honghui Zhang
The MTCMOS of PCIe Host for MT2712 and MT7622 will be off when system
suspend, and all the internal control register will be reset after system
resume. The PCIe link should be re-established and the related control
register values should be re-set after system resume.
Signed-
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