Re: [PATCH v3 2/2] i2c: cadence: Check for errata condition involving master receive

2014-12-05 Thread Sören Brinkmann
Hi Harini, On Fri, 2014-12-05 at 01:38PM +0530, Harini Katakam wrote: > Cadence I2C controller has the following bugs: > - completion indication is not given to the driver at the end of > a read/receive transfer with HOLD bit set. > - Invalid read transaction are generated on the bus when HW timeo

Re: [PATCH v3 2/2] i2c: cadence: Check for errata condition involving master receive

2014-12-05 Thread rajeev kumar
On Fri, Dec 5, 2014 at 1:38 PM, Harini Katakam wrote: > Cadence I2C controller has the following bugs: > - completion indication is not given to the driver at the end of > a read/receive transfer with HOLD bit set. > - Invalid read transaction are generated on the bus when HW timeout > condition o

[PATCH v3 2/2] i2c: cadence: Check for errata condition involving master receive

2014-12-05 Thread Harini Katakam
Cadence I2C controller has the following bugs: - completion indication is not given to the driver at the end of a read/receive transfer with HOLD bit set. - Invalid read transaction are generated on the bus when HW timeout condition occurs with HOLD bit set. As a result of the above, if a set of m