Re: [PATCH v3 2/2] dma: Add Xilinx zynqmp dma engine driver support

2015-07-17 Thread punnaiah choudary kalluri
On Fri, Jul 17, 2015 at 2:38 PM, Vinod Koul wrote: > On Fri, Jul 17, 2015 at 09:54:48AM +0530, punnaiah choudary kalluri wrote: > your MUA is wrapping lines funny, please fix it > >> >> I have explored using the virt-dma to reduce the common list processing, >> >> But >> >> in this driver descrip

Re: [PATCH v3 2/2] dma: Add Xilinx zynqmp dma engine driver support

2015-07-17 Thread Vinod Koul
On Fri, Jul 17, 2015 at 09:54:48AM +0530, punnaiah choudary kalluri wrote: your MUA is wrapping lines funny, please fix it > >> I have explored using the virt-dma to reduce the common list processing, > >> But > >> in this driver descriptor processing and cleaning is happening inside > >> the tas

Re: [PATCH v3 2/2] dma: Add Xilinx zynqmp dma engine driver support

2015-07-16 Thread punnaiah choudary kalluri
On Fri, Jul 17, 2015 at 8:35 AM, Vinod Koul wrote: > On Fri, Jul 17, 2015 at 06:22:42AM +0530, punnaiah choudary kalluri wrote: >> On Thu, Jul 16, 2015 at 6:05 PM, Vinod Koul wrote: >> > On Tue, Jun 16, 2015 at 08:04:43AM +0530, Punnaiah Choudary Kalluri wrote: >> >> +/* Register Offsets */ >> >>

Re: [PATCH v3 2/2] dma: Add Xilinx zynqmp dma engine driver support

2015-07-16 Thread Vinod Koul
On Fri, Jul 17, 2015 at 06:22:42AM +0530, punnaiah choudary kalluri wrote: > On Thu, Jul 16, 2015 at 6:05 PM, Vinod Koul wrote: > > On Tue, Jun 16, 2015 at 08:04:43AM +0530, Punnaiah Choudary Kalluri wrote: > >> +/* Register Offsets */ > >> +#define ISR 0x100 > >> +#define

Re: [PATCH v3 2/2] dma: Add Xilinx zynqmp dma engine driver support

2015-07-16 Thread punnaiah choudary kalluri
On Thu, Jul 16, 2015 at 6:05 PM, Vinod Koul wrote: > On Tue, Jun 16, 2015 at 08:04:43AM +0530, Punnaiah Choudary Kalluri wrote: >> +/* Register Offsets */ >> +#define ISR 0x100 >> +#define IMR 0x104 >> +#define IER 0x108 >>

Re: [PATCH v3 2/2] dma: Add Xilinx zynqmp dma engine driver support

2015-07-16 Thread Vinod Koul
On Tue, Jun 16, 2015 at 08:04:43AM +0530, Punnaiah Choudary Kalluri wrote: > +/* Register Offsets */ > +#define ISR 0x100 > +#define IMR 0x104 > +#define IER 0x108 > +#define IDS 0x10C > +#define CTR

[PATCH v3 2/2] dma: Add Xilinx zynqmp dma engine driver support

2015-07-13 Thread Punnaiah Choudary Kalluri
Added the basic driver for zynqmp dma engine used in Zynq UltraScale+ MPSoC. The initial release of this driver supports only memory to memory transfers. Signed-off-by: Punnaiah Choudary Kalluri --- Changes in v3: - Modified the zynqmp_dma_chan_is_idle function return type to bool Changes in v2:

[PATCH v3 2/2] dma: Add Xilinx zynqmp dma engine driver support

2015-06-15 Thread Punnaiah Choudary Kalluri
Added the basic driver for zynqmp dma engine used in Zynq UltraScale+ MPSoC. The initial release of this driver supports only memory to memory transfers. Signed-off-by: Punnaiah Choudary Kalluri --- Changes in v3: - Modified the zynqmp_dma_chan_is_idle function return type to bool Changes in v2