On Wed, Oct 09, 2019 at 11:21:41AM +0200, Paolo Bonzini wrote:
> On 13/09/19 21:01, Suthikulpanit, Suravee wrote:
> > /*
> > +* In case APICv accelerate EOI write and do not trap,
> > +* in-kernel IOAPIC will not be able to receive the EOI.
> > +* In this case, we do lazy update of
On 13/09/19 21:01, Suthikulpanit, Suravee wrote:
> /*
> + * In case APICv accelerate EOI write and do not trap,
> + * in-kernel IOAPIC will not be able to receive the EOI.
> + * In this case, we do lazy update of the pending EOI when
> + * trying to set IOAPIC irq.
> +
In-kernel IOAPIC does not receive EOI with AMD SVM AVIC
since the processor accelerate write to APIC EOI register and
does not trap if the interrupt is edge-triggered.
Workaround this by lazy check for pending APIC EOI at the time when
setting new IOPIC irq, and update IOAPIC EOI if no pending API
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