Hi Mark,
On Fri, Apr 11, 2014 at 9:06 AM, Harini Katakam
wrote:
> Hi Mark,
>
> On Fri, Apr 11, 2014 at 4:18 AM, Mark Brown wrote:
>> On Thu, Apr 10, 2014 at 05:43:49PM +0530, Harini Katakam wrote:
>>> Add driver for Cadence SPI controller. This is used in Xilinx Zynq.
>>
>> This looks mostly goo
Hi Mark,
On Fri, Apr 11, 2014 at 4:18 AM, Mark Brown wrote:
> On Thu, Apr 10, 2014 at 05:43:49PM +0530, Harini Katakam wrote:
>> Add driver for Cadence SPI controller. This is used in Xilinx Zynq.
>
> This looks mostly good, the issues below are very small.
>
>> +static int __maybe_unused cdns_sp
On Thu, Apr 10, 2014 at 05:43:49PM +0530, Harini Katakam wrote:
> Add driver for Cadence SPI controller. This is used in Xilinx Zynq.
This looks mostly good, the issues below are very small.
> +static int __maybe_unused cdns_spi_suspend(struct device *dev)
> +{
> + struct platform_device *pde
Hi Mark,
On Thu, Apr 10, 2014 at 5:51 PM, Mark Brown wrote:
> On Thu, Apr 10, 2014 at 05:43:49PM +0530, Harini Katakam wrote:
>
>> Firstly, the timeout value obtained from this is a too low.
>> This timeout is typically used for an error conditions such as
>> hardware hang etc. and using a value
On Thu, Apr 10, 2014 at 05:43:49PM +0530, Harini Katakam wrote:
> Firstly, the timeout value obtained from this is a too low.
> This timeout is typically used for an error conditions such as
> hardware hang etc. and using a value >1*HZ would be better.
> This driver used to use similar timeout and
Add driver for Cadence SPI controller. This is used in Xilinx Zynq.
Signed-off-by: Harini Katakam
---
Here is the v3 series but I have one concern.
The recent change in spi-core to use wait_for_completion_timeout
uses a timeout value calculated as follows:
ms = xfer->len * 8 * 1000/xfer->speed_h
6 matches
Mail list logo
