On Thu, Feb 23, 2017 at 04:31:34AM +1100, Richard Henderson wrote:
> On 02/23/2017 01:22 AM, Stafford Horne wrote:
> > > static inline int __atomic_add_unless(atomic_t *v, int a, int u)
> > > {
> > > int old, tmp;
> > >
> > > __asm__ __volatile__(
> > > "1: l.lwa %0, 0(%2)
On 02/23/2017 01:22 AM, Stafford Horne wrote:
static inline int __atomic_add_unless(atomic_t *v, int a, int u)
{
int old, tmp;
__asm__ __volatile__(
"1: l.lwa %0, 0(%2) \n"
" l.sfeq %0, %4 \n"
" l.b
On Wed, Feb 22, 2017 at 12:27:37PM +0100, Peter Zijlstra wrote:
> On Wed, Feb 22, 2017 at 04:11:38AM +0900, Stafford Horne wrote:
> > +#define atomic_add_return atomic_add_return
> > +#define atomic_sub_return atomic_sub_return
> > +#define atomic_fetch_add atomic_fetch_add
> > +#define atomic_
On Wed, Feb 22, 2017 at 04:11:38AM +0900, Stafford Horne wrote:
> +#define atomic_add_returnatomic_add_return
> +#define atomic_sub_returnatomic_sub_return
> +#define atomic_fetch_add atomic_fetch_add
> +#define atomic_fetch_sub atomic_fetch_sub
> +#define atomic_fetch_and atomi
From: Stefan Kristiansson
Using the l.lwa and l.swa atomic instruction pair.
Most openrisc processor cores provide these instructions now. If the
instructions are not available emulation is provided.
Cc: Peter Zijlstra
Signed-off-by: Stefan Kristiansson
[sho...@gmail.com: remove OPENRISC_HAVE_
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