Re: [PATCH v3 09/12] RISC-V: User WRITE_ONCE instead of direct access

On Thu, Sep 06, 2018 at 01:05:32AM -0700, Atish Patra wrote: > The secondary harts spin on couple of per cpu variables until both of > these are non-zero so it's not necessary to have any ordering here. > However, WRITE_ONCE should be used to avoid tearing. We normally pair WRITE_ONCE with READ_ON

[PATCH v3 09/12] RISC-V: User WRITE_ONCE instead of direct access

The secondary harts spin on couple of per cpu variables until both of these are non-zero so it's not necessary to have any ordering here. However, WRITE_ONCE should be used to avoid tearing. Signed-off-by: Atish Patra --- arch/riscv/kernel/smpboot.c | 5 +++-- 1 file changed, 3 insertions(+), 2