Re: [PATCH v3 0/7] MIPS: perf: MT fixes and improvements

2018-04-23 Thread Matt Redfearn
On 20/04/18 23:51, Florian Fainelli wrote: On 04/20/2018 03:23 AM, Matt Redfearn wrote: This series addresses a few issues with how the MIPS performance counters code supports the hardware multithreading MT ASE. Firstly, implementations of the MT ASE may implement performance counters per cor

Re: [PATCH v3 0/7] MIPS: perf: MT fixes and improvements

2018-04-20 Thread Florian Fainelli
On 04/20/2018 03:23 AM, Matt Redfearn wrote: > This series addresses a few issues with how the MIPS performance > counters code supports the hardware multithreading MT ASE. > > Firstly, implementations of the MT ASE may implement performance > counters > per core or per thread(TC). MIPS Techologie

[PATCH v3 0/7] MIPS: perf: MT fixes and improvements

2018-04-20 Thread Matt Redfearn
This series addresses a few issues with how the MIPS performance counters code supports the hardware multithreading MT ASE. Firstly, implementations of the MT ASE may implement performance counters per core or per thread(TC). MIPS Techologies implementations signal this via a bit in the implmentat