Re: [PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds

2017-05-09 Thread Robert Richter
On 08.05.17 20:45:36, Linu Cherian wrote: > On Sat May 06, 2017 at 12:22:50AM +0200, Robert Richter wrote: > > On 05.05.17 17:38:04, Geetha sowjanya wrote: > > > From: Linu Cherian > > > > > > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > > > 1. Errata ID #74 > > >SMMU reg

Re: [PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds

2017-05-08 Thread Linu Cherian
On Sat May 06, 2017 at 12:22:50AM +0200, Robert Richter wrote: > On 05.05.17 17:38:04, Geetha sowjanya wrote: > > From: Linu Cherian > > > > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > > 1. Errata ID #74 > >SMMU register alias Page 1 is not implemented > > 2. Errata ID #

Re: [PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds

2017-05-05 Thread Robert Richter
On 05.05.17 17:38:04, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 >SMMU register alias Page 1 is not implemented > 2. Errata ID #126 >SMMU doesnt support unique IRQ lines and also MSI for gerror, >

[PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds

2017-05-05 Thread Geetha sowjanya
From: Linu Cherian Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. 1. Errata ID #74 SMMU register alias Page 1 is not implemented 2. Errata ID #126 SMMU doesnt support unique IRQ lines and also MSI for gerror, eventq and cmdq-sync The following patchset does software wo