On Mon, Oct 02, 2017 at 06:30:41PM +0800, Miles Chen wrote:
> ARCHs like metag and xtensa define their mappings (non-vmalloc and
> non-linear) for dma allocation.
metag basically is a reimplementation of the vmalloc map mechanism
that should be easy to consolidate into the common one :( xtensa
ha
On Sun, 2017-10-01 at 10:04 +0200, Christoph Hellwig wrote:
> On Wed, Sep 27, 2017 at 11:23:52AM +0100, Robin Murphy wrote:
> > > I found that debug_dma_alloc_coherent() and debug_dma_free_coherent()
> > > assume that dma_alloc_coherent() always returns a linear address.
> > > However it's possible
On Wed, Sep 27, 2017 at 11:23:52AM +0100, Robin Murphy wrote:
> > I found that debug_dma_alloc_coherent() and debug_dma_free_coherent()
> > assume that dma_alloc_coherent() always returns a linear address.
> > However it's possible that dma_alloc_coherent() returns a non-linear
> > address. In this
[+DMA maintainers]
On 27/09/17 04:48, miles.c...@mediatek.com wrote:
> From: Miles Chen
>
> dma-debug reports the following warning:
>
> [name:panic&]WARNING: CPU: 3 PID: 298 at kernel-4.4/lib/dma-debug.c:604
> debug _dma_assert_idle+0x1a8/0x230()
> DMA-API: cpu touching an active dma mapped ca
From: Miles Chen
dma-debug reports the following warning:
[name:panic&]WARNING: CPU: 3 PID: 298 at kernel-4.4/lib/dma-debug.c:604
debug _dma_assert_idle+0x1a8/0x230()
DMA-API: cpu touching an active dma mapped cacheline [cln=0x0882300]
CPU: 3 PID: 298 Comm: vold Tainted: GW O4.4
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