Re: [PATCH v3] PCI/ASPM: Enable ASPM for bridge-to-bridge link

2020-05-07 Thread Bjorn Helgaas
On Wed, May 06, 2020 at 01:34:21AM +0800, Kai-Heng Feng wrote: > The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power > state deeper than PC3 due to disabled ASPM, consumes lots of unnecessary > power. On Windows ASPM L1 is enabled on the device and its upstream > bridge, so it can

Re: [PATCH v3] PCI/ASPM: Enable ASPM for bridge-to-bridge link

2020-05-07 Thread Mika Westerberg
On Wed, May 06, 2020 at 04:29:47PM -0500, Bjorn Helgaas wrote: > On Wed, May 06, 2020 at 09:14:38AM +0300, Mika Westerberg wrote: > > On Wed, May 06, 2020 at 01:34:21AM +0800, Kai-Heng Feng wrote: > > > The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power > > > state deeper than PC3

Re: [PATCH v3] PCI/ASPM: Enable ASPM for bridge-to-bridge link

2020-05-06 Thread Bjorn Helgaas
On Wed, May 06, 2020 at 09:14:38AM +0300, Mika Westerberg wrote: > On Wed, May 06, 2020 at 01:34:21AM +0800, Kai-Heng Feng wrote: > > The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power > > state deeper than PC3 due to disabled ASPM, consumes lots of unnecessary > > power. On Windo

Re: [PATCH v3] PCI/ASPM: Enable ASPM for bridge-to-bridge link

2020-05-05 Thread Mika Westerberg
On Wed, May 06, 2020 at 01:34:21AM +0800, Kai-Heng Feng wrote: > The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power > state deeper than PC3 due to disabled ASPM, consumes lots of unnecessary > power. On Windows ASPM L1 is enabled on the device and its upstream > bridge, so it can

[PATCH v3] PCI/ASPM: Enable ASPM for bridge-to-bridge link

2020-05-05 Thread Kai-Heng Feng
The TI PCIe-to-PCI bridge prevents the Intel SoC from entering power state deeper than PC3 due to disabled ASPM, consumes lots of unnecessary power. On Windows ASPM L1 is enabled on the device and its upstream bridge, so it can make the Intel SoC reach PC8 or PC10 to save lots of power. In short,