On Thu, Jun 27, 2019 at 5:18 AM Jiong Wang wrote:
>
> #define BPF_ZEXT_REG(DST)
> ((struct bpf_insn) {
> .code = BPF_ALU | BPF_MOV | BPF_X
>
> So it can't be BPF_ALU64. It is safe to remove this chunk of code.
>
Thanks! I'll fix this in the next revision.
- Luke
Luke Nelson writes:
> +
> +static int emit_insn(const struct bpf_insn *insn,
> + struct rv_jit_context *ctx,
> + bool extra_pass)
> +{
> + int rvoff, i = insn - ctx->prog->insnsi;
> + u8 code = insn->code;
> + s16 off = insn->off;
> + s32 imm =
From: Luke Nelson
This is an eBPF JIT for RV32G, adapted from the JIT for RV64G.
There are two main changes required for this to work compared to the
RV64 JIT.
First, eBPF registers are 64-bit, while RV32G registers are 32-bit.
BPF registers either map directly to 2 RISC-V registers, or reside
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