On 9/15/2012 10:00 AM, David Brown wrote:
On Sat, Sep 15, 2012 at 12:41:53AM -0700, Rohit Vaswani wrote:
On some hardware, the timer deasserts the interrupt when a
new TVAL is written only when the enable bit is cleared.
Hence explicitly disable the timer and then program the
TVAL followed by en
On Sat, Sep 15, 2012 at 12:41:53AM -0700, Rohit Vaswani wrote:
> On some hardware, the timer deasserts the interrupt when a
> new TVAL is written only when the enable bit is cleared.
> Hence explicitly disable the timer and then program the
> TVAL followed by enabling the timer.
> If this order is
On some hardware, the timer deasserts the interrupt when a
new TVAL is written only when the enable bit is cleared.
Hence explicitly disable the timer and then program the
TVAL followed by enabling the timer.
If this order is not followed, there are chances that
you would not receive any timer inte
3 matches
Mail list logo