Re: [PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

2016-09-02 Thread Suzuki K Poulose
On 26/08/16 18:00, Catalin Marinas wrote: On Fri, Aug 26, 2016 at 05:16:27PM +0100, Will Deacon wrote: On Fri, Aug 26, 2016 at 02:08:01PM +0100, Suzuki K Poulose wrote: On 26/08/16 14:04, Suzuki K Poulose wrote: It might be worth looking to see if we can pass the ctr as an extra parameter to

Re: [PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

2016-08-26 Thread Catalin Marinas
On Fri, Aug 26, 2016 at 05:16:27PM +0100, Will Deacon wrote: > On Fri, Aug 26, 2016 at 02:08:01PM +0100, Suzuki K Poulose wrote: > > On 26/08/16 14:04, Suzuki K Poulose wrote: > > >On 26/08/16 12:03, Ard Biesheuvel wrote: > > >>IMO, this is a pattern that we should avoid: you are introducing one >

Re: [PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

2016-08-26 Thread Ard Biesheuvel
On 26 August 2016 at 17:16, Will Deacon wrote: > On Fri, Aug 26, 2016 at 02:08:01PM +0100, Suzuki K Poulose wrote: >> On 26/08/16 14:04, Suzuki K Poulose wrote: >> >On 26/08/16 12:03, Ard Biesheuvel wrote: >> >>IMO, this is a pattern that we should avoid: you are introducing one >> >>instance now,

Re: [PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

2016-08-26 Thread Will Deacon
On Fri, Aug 26, 2016 at 02:08:01PM +0100, Suzuki K Poulose wrote: > On 26/08/16 14:04, Suzuki K Poulose wrote: > >On 26/08/16 12:03, Ard Biesheuvel wrote: > >>IMO, this is a pattern that we should avoid: you are introducing one > >>instance now, which will make it hard to say no to the next one in

Re: [PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

2016-08-26 Thread Suzuki K Poulose
On 26/08/16 12:03, Ard Biesheuvel wrote: Hello Suzuki, For faster access (i.e, avoiding to lookup the system wide value of CTR_EL0 via read_system_reg), we keep track of the pointer to table entry for CTR_EL0 in the CPU feature infrastructure. IIUC it is the runtime sorting of the arm64_f

Re: [PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

2016-08-26 Thread Suzuki K Poulose
On 26/08/16 14:04, Suzuki K Poulose wrote: On 26/08/16 12:03, Ard Biesheuvel wrote: Hello Suzuki, For faster access (i.e, avoiding to lookup the system wide value of CTR_EL0 via read_system_reg), we keep track of the pointer to table entry for CTR_EL0 in the CPU feature infrastructure. I

Re: [PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

2016-08-26 Thread Ard Biesheuvel
Hello Suzuki, On 26 August 2016 at 11:23, Suzuki K Poulose wrote: > Systems with differing CPU i-cache/d-cache line sizes can cause > problems with the cache management by software when the execution > is migrated from one to another. Usually, the application reads > the cache size on a CPU and t

[PATCH v2 9/9] arm64: Work around systems with mismatched cache line sizes

2016-08-26 Thread Suzuki K Poulose
Systems with differing CPU i-cache/d-cache line sizes can cause problems with the cache management by software when the execution is migrated from one to another. Usually, the application reads the cache size on a CPU and then uses that length to perform cache operations. However, if it gets migrat