>>
>>
>> Is this specified anywhere in SDM as a requirement for x86 OS? If so,
>> maybe provide a pointer to support this.
>
>
> In the case of the Intel manuals, it mentions in several places that
> SS.DPL=CPL. All the mentions are in the VMX sections of the manual, though
> I've found non-Intel
On Thu, May 15, 2014 at 06:51:31PM +0200, Paolo Bonzini wrote:
> CS.RPL is not equal to the CPL in the few instructions between
> setting CR0.PE and reloading CS. And CS.DPL is also not equal
> to the CPL for conforming code segments.
>
> However, SS.DPL *is* always equal to the CPL except for th
Il 26/05/2014 01:21, Wei Huang ha scritto:
CS.RPL is not equal to the CPL in the few instructions between
setting CR0.PE and reloading CS. And CS.DPL is also not equal
to the CPL for conforming code segments.
Out of my curiousity, could you elaborate the problem of this
CPL gap window, such as
> CS.RPL is not equal to the CPL in the few instructions between
> setting CR0.PE and reloading CS. And CS.DPL is also not equal
> to the CPL for conforming code segments.
Out of my curiousity, could you elaborate the problem of this
CPL gap window, such as breaking any VMs or tests? From Linux k
CS.RPL is not equal to the CPL in the few instructions between
setting CR0.PE and reloading CS. And CS.DPL is also not equal
to the CPL for conforming code segments.
However, SS.DPL *is* always equal to the CPL except for the weird
case of SYSRET on AMD processors, which sets SS.DPL=SS.RPL from t
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