Re: [PATCH v2 3/6] riscv: ftrace: prepare ftrace for atomic code patching

Björn Töpel writes: > Andy Chiu writes: > >> We use an AUIPC+JALR pair to jump into a ftrace trampoline. Since >> instruction fetch can break down to 4 byte at a time, it is impossible >> to update two instructions without a race. In order to mitigate it, we >> initialize the patchable entry to

Re: [PATCH v2 3/6] riscv: ftrace: prepare ftrace for atomic code patching

Andy Chiu writes: > We use an AUIPC+JALR pair to jump into a ftrace trampoline. Since > instruction fetch can break down to 4 byte at a time, it is impossible > to update two instructions without a race. In order to mitigate it, we > initialize the patchable entry to AUIPC + NOP4. Then, the run-t

[PATCH v2 3/6] riscv: ftrace: prepare ftrace for atomic code patching

We use an AUIPC+JALR pair to jump into a ftrace trampoline. Since instruction fetch can break down to 4 byte at a time, it is impossible to update two instructions without a race. In order to mitigate it, we initialize the patchable entry to AUIPC + NOP4. Then, the run-time code patching can change