Re: [PATCH v2 3/3] riscv: Add cache information in AUX vector

Hi Zong, url: https://github.com/0day-ci/linux/commits/Zong-Li/Get-cache-information-from-userland/20200827-162439 base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 15bc20c6af4ceee97a1f90b43c0e386643c071b4 config: riscv-randconfig-m031-20200828 (attached as .config) c

Re: [PATCH v2 3/3] riscv: Add cache information in AUX vector

Hi Zong, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on linus/master] [also build test WARNING on v5.9-rc2 next-20200827] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented

[PATCH v2 3/3] riscv: Add cache information in AUX vector

There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. Currently, AT_L1I_X, AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall could use them to get information of cache through AUX vector. The result of 'getconf