On Sun, 13 Sep 2015, Krzysztof Kozlowski wrote:
> You acked this patch. However finally it did not go through other tree
> so maybe you could pick it up for 4.4?
>
> If you want I could reabse and resend it.
Yes, please rebase and resend.
> 2015-08-11 19:09 GMT+09:00 Krzysztof Kozlowski :
> >
>
Hi Lee,
You acked this patch. However finally it did not go through other tree
so maybe you could pick it up for 4.4?
If you want I could reabse and resend it.
Best regards,
Krzysztof
2015-08-11 19:09 GMT+09:00 Krzysztof Kozlowski :
>
> On Odroid XU3 board (with S2MPS11 PMIC) the PWRHOLD bit i
On Odroid XU3 board (with S2MPS11 PMIC) the PWRHOLD bit in CTRL1
register must be manually set to 0 before initiating power off sequence.
One of usual power down methods for Exynos based devices looks like:
1. PWRHOLD pin of PMIC is connected to PSHOLD of Exynos.
2. Exynos holds up this pin during
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