Re: [PATCH v2 16/19] clk: tegra: pll: Add Set_default logic

2015-05-11 Thread Rhyland Klein
On 5/11/2015 7:50 AM, Peter De Schrijver wrote: > On Thu, Apr 30, 2015 at 11:31:22AM -0400, Rhyland Klein wrote: >> On 4/30/2015 6:12 AM, Peter De Schrijver wrote: >>> On Wed, Apr 29, 2015 at 01:21:46PM -0400, Rhyland Klein wrote: From: Bill Huang Add logic which (if specified for a

Re: [PATCH v2 16/19] clk: tegra: pll: Add Set_default logic

2015-05-11 Thread Peter De Schrijver
On Thu, Apr 30, 2015 at 11:31:22AM -0400, Rhyland Klein wrote: > On 4/30/2015 6:12 AM, Peter De Schrijver wrote: > > On Wed, Apr 29, 2015 at 01:21:46PM -0400, Rhyland Klein wrote: > >> From: Bill Huang > >> > >> Add logic which (if specified for a pll) can verify that a PLL is set > >> to the prop

Re: [PATCH v2 16/19] clk: tegra: pll: Add Set_default logic

2015-04-30 Thread Rhyland Klein
On 4/30/2015 6:12 AM, Peter De Schrijver wrote: > On Wed, Apr 29, 2015 at 01:21:46PM -0400, Rhyland Klein wrote: >> From: Bill Huang >> >> Add logic which (if specified for a pll) can verify that a PLL is set >> to the proper default value and if not can set it. This can be >> specified per PLL as

Re: [PATCH v2 16/19] clk: tegra: pll: Add Set_default logic

2015-04-30 Thread Peter De Schrijver
On Wed, Apr 29, 2015 at 01:21:46PM -0400, Rhyland Klein wrote: > From: Bill Huang > > Add logic which (if specified for a pll) can verify that a PLL is set > to the proper default value and if not can set it. This can be > specified per PLL as each will have different default values. > Why can'

[PATCH v2 16/19] clk: tegra: pll: Add Set_default logic

2015-04-29 Thread Rhyland Klein
From: Bill Huang Add logic which (if specified for a pll) can verify that a PLL is set to the proper default value and if not can set it. This can be specified per PLL as each will have different default values. Signed-off-by: Bill Huang --- v2: - Remove MACRO for PLL_MISC_CHECK_DEFAULT as su