On 5 March 2015 at 11:58, Viresh Kumar wrote:
> On 5 March 2015 at 09:02, Pi-Cheng Chen wrote:
>> In the case of Mediatek SoC, the intermediate frequency might not be one
>> entry
>> of OPP table. To elaborate, the source clock node of the CPUs/Cluster on
>> Mediatek SoC is a mux. The mux has se
On 5 March 2015 at 09:02, Pi-Cheng Chen wrote:
> In the case of Mediatek SoC, the intermediate frequency might not be one entry
> of OPP table. To elaborate, the source clock node of the CPUs/Cluster on
> Mediatek SoC is a mux. The mux has several PLLs as parents. When we are
> doing CPU frequency
Hi Viresh,
Thanks for reviewing. Please see my reply below:
On 4 March 2015 at 18:15, Viresh Kumar wrote:
> On 4 March 2015 at 14:19, pi-cheng.chen wrote:
>> In this patch, CPU clock/power domain information is added into the
>> platform_data of cpufreq-dt so that cpufreq-dt driver could check
On 4 March 2015 at 15:45, Viresh Kumar wrote:
>> +struct cpufreq_cpu_domain {
>> + struct list_head node;
>> + cpumask_t cpus;
>> + unsigned long intermediate_freq;
>
> This should come from DT instead of platform data.
Well, we are getting fixed this in OPP bindings now, so for
On 4 March 2015 at 14:19, pi-cheng.chen wrote:
> In this patch, CPU clock/power domain information is added into the
> platform_data of cpufreq-dt so that cpufreq-dt driver could check with CPUs
> share clock/power. Also, intermediate frequency support is added in this
You should have separate pa
In this patch, CPU clock/power domain information is added into the
platform_data of cpufreq-dt so that cpufreq-dt driver could check with CPUs
share clock/power. Also, intermediate frequency support is added in this
version. Since the program flows of .target_index and .target_intermediate
are qu
6 matches
Mail list logo
