On Tue, Jun 13, 2017 at 05:51:42PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年6月13日 GMT+08:00 下午3:44:32, Maxime Ripard
> 写到:
> >On Sun, Jun 11, 2017 at 02:43:42PM +0800, icen...@aosc.io wrote:
> >> 在 2017-06-07 17:38,Maxime Ripard 写道:
> >> > On Mon, Jun 05, 2017 at 12:01:45AM +0800, Icenowy Zheng
于 2017年6月13日 GMT+08:00 下午3:44:32, Maxime Ripard
写到:
>On Sun, Jun 11, 2017 at 02:43:42PM +0800, icen...@aosc.io wrote:
>> 在 2017-06-07 17:38,Maxime Ripard 写道:
>> > On Mon, Jun 05, 2017 at 12:01:45AM +0800, Icenowy Zheng wrote:
>> > > Allwinner H3 features a TV encoder similar to the one in earli
On Sun, Jun 11, 2017 at 02:43:42PM +0800, icen...@aosc.io wrote:
> 在 2017-06-07 17:38,Maxime Ripard 写道:
> > On Mon, Jun 05, 2017 at 12:01:45AM +0800, Icenowy Zheng wrote:
> > > Allwinner H3 features a TV encoder similar to the one in earlier SoCs,
> > > but has a internal fixed clock divider that d
在 2017-06-07 17:38,Maxime Ripard 写道:
On Mon, Jun 05, 2017 at 12:01:45AM +0800, Icenowy Zheng wrote:
Allwinner H3 features a TV encoder similar to the one in earlier SoCs,
but has a internal fixed clock divider that divides the TCON1 clock
(called TVE clock in datasheet) by 11.
Add support for i
On Mon, Jun 05, 2017 at 12:01:45AM +0800, Icenowy Zheng wrote:
> Allwinner H3 features a TV encoder similar to the one in earlier SoCs,
> but has a internal fixed clock divider that divides the TCON1 clock
> (called TVE clock in datasheet) by 11.
>
> Add support for it.
>
> Signed-off-by: Icenowy
Allwinner H3 features a TV encoder similar to the one in earlier SoCs,
but has a internal fixed clock divider that divides the TCON1 clock
(called TVE clock in datasheet) by 11.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Quirk part rewritten.
drivers/gpu/drm/sun4i/su
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