On Wed, Sep 07, 2016 at 01:24:23PM +0200, Peter Zijlstra wrote:
> > +/*
> > + * Ordering barriers:
> > + * - Every synchronizable specified memory instruction (loads or stores or
> > both)
> > + * that occurs in the instruction stream before the SYNC instruction must
> > + * reach a stage in t
This seems to be verbatim copies of the text from the manual. A few
questions below.
On Wed, Sep 07, 2016 at 10:45:13AM +0100, Matt Redfearn wrote:
> +/*
> + * Completion barriers:
> + * - Every synchronizable specified memory instruction (loads or stores or
> both)
> + * that occurs in the i
Add the definitions of sync stype 0 (global completion barrier) and sync
stype 0x10 (local ordering barrier) to barrier.h for use with the sync
instruction.
These types are defined by the MIPS Instruction Set since R2 of the
architecture and are documented in document MD00087 table 6.5.
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