Re: [PATCH v2 04/31] arm64: MMU definitions

2012-08-17 Thread Tony Lindgren
* Catalin Marinas [120817 02:21]: > On Fri, Aug 17, 2012 at 10:04:52AM +0100, Tony Lindgren wrote: > > * Catalin Marinas [120814 10:57]: > > > The virtual memory layout is described in > > > Documentation/arm64/memory.txt. This patch adds the MMU definitions for > > > the 4KB and 64KB translation

Re: [PATCH v2 04/31] arm64: MMU definitions

2012-08-17 Thread Catalin Marinas
On Fri, Aug 17, 2012 at 10:04:52AM +0100, Tony Lindgren wrote: > * Catalin Marinas [120814 10:57]: > > The virtual memory layout is described in > > Documentation/arm64/memory.txt. This patch adds the MMU definitions for > > the 4KB and 64KB translation table configurations. The SECTION_SIZE is >

Re: [PATCH v2 04/31] arm64: MMU definitions

2012-08-17 Thread Tony Lindgren
* Catalin Marinas [120814 10:57]: > The virtual memory layout is described in > Documentation/arm64/memory.txt. This patch adds the MMU definitions for > the 4KB and 64KB translation table configurations. The SECTION_SIZE is > 2MB with 4KB page and 512MB with 64KB page configuration. > > PHYS_OFF

Re: [PATCH v2 04/31] arm64: MMU definitions

2012-08-15 Thread Catalin Marinas
On Wed, Aug 15, 2012 at 05:34:46PM +0100, Geert Uytterhoeven wrote: > On Wed, Aug 15, 2012 at 3:30 PM, Arnd Bergmann wrote: > >> +#define TCR_IPS_40BIT(2 << 32) > > By default, constants are int, i.e. 32-bit. So you must write > > 2ULL << 32 > > >> +#define TCR_ASID16

Re: [PATCH v2 04/31] arm64: MMU definitions

2012-08-15 Thread Geert Uytterhoeven
On Wed, Aug 15, 2012 at 3:30 PM, Arnd Bergmann wrote: >> +#define TCR_IPS_40BIT(2 << 32) By default, constants are int, i.e. 32-bit. So you must write 2ULL << 32 >> +#define TCR_ASID16 (1 << 36) 1ULL > As a matter of coding style, I would much prefer tables like this

Re: [PATCH v2 04/31] arm64: MMU definitions

2012-08-15 Thread Catalin Marinas
Hi Arnd, On Wed, Aug 15, 2012 at 02:30:01PM +0100, Arnd Bergmann wrote: > On Tuesday 14 August 2012, Catalin Marinas wrote: > > +/* > > + * TCR flags. > > + */ > > +#define TCR_TxSZ(x)(((64 - (x)) << 16) | ((64 - (x)) << 0)) > > +#define TCR_IRGN_NC((0 << 8) | (0 <<

Re: [PATCH v2 04/31] arm64: MMU definitions

2012-08-15 Thread Arnd Bergmann
On Tuesday 14 August 2012, Catalin Marinas wrote: > > +/* > + * TCR flags. > + */ > +#define TCR_TxSZ(x) (((64 - (x)) << 16) | ((64 - (x)) << 0)) > +#define TCR_IRGN_NC ((0 << 8) | (0 << 24)) > +#define TCR_IRGN_WBWA((1 << 8) | (1 << 24)) > +#define TCR_IRGN_WT

[PATCH v2 04/31] arm64: MMU definitions

2012-08-14 Thread Catalin Marinas
The virtual memory layout is described in Documentation/arm64/memory.txt. This patch adds the MMU definitions for the 4KB and 64KB translation table configurations. The SECTION_SIZE is 2MB with 4KB page and 512MB with 64KB page configuration. PHYS_OFFSET is calculated at run-time and stored in a v