Re: [PATCH v2 02/10] clk: ccu-sun8i-a33: Add CLK_SET_RATE_PARENT to ac-dig

2017-01-17 Thread Mylene Josserand
Hi, On 17/01/2017 17:44, Maxime Ripard wrote: Hi, On Tue, Jan 17, 2017 at 03:02:22PM +0100, Mylène Josserand wrote: The audio DAI needs to set the clock rates of the ac-dig clock. To make it possible, the parent PLL audio clock rates should also be changed. This is possible via "CLK_SET_RATE_P

Re: [PATCH v2 02/10] clk: ccu-sun8i-a33: Add CLK_SET_RATE_PARENT to ac-dig

2017-01-17 Thread Maxime Ripard
Hi, On Tue, Jan 17, 2017 at 03:02:22PM +0100, Mylène Josserand wrote: > The audio DAI needs to set the clock rates of the ac-dig clock. > To make it possible, the parent PLL audio clock rates should > also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. > > Signed-off-by: Mylène Joss

[PATCH v2 02/10] clk: ccu-sun8i-a33: Add CLK_SET_RATE_PARENT to ac-dig

2017-01-17 Thread Mylène Josserand
The audio DAI needs to set the clock rates of the ac-dig clock. To make it possible, the parent PLL audio clock rates should also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. Signed-off-by: Mylène Josserand --- drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +- 1 file changed, 1 insert