Re: [PATCH v2] x86/centaur: report correct CPU/cache topology

alliance.com; cooper...@zhaoxin.com; qiyuanw...@zhaoxin.com; > benjamin...@viatech.com; luke...@viacpu.com; tim...@zhaoxin.com > Subject: Re: [PATCH v2] x86/centaur: report correct CPU/cache topology > > On Wed, 25 Apr 2018, David Wang wrote: > > > > +static void early_in

Re: [PATCH v2] x86/centaur: report correct CPU/cache topology

On Wed, 25 Apr 2018, David Wang wrote: > > +static void early_init_centaur_mc(struct cpuinfo_x86 *c) > +{ > +#ifdef CONFIG_SMP > + unsigned int eax, ebx, ecx, edx; > + > + if (c->cpuid_level < 4) > + return; > + > + cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); > + if (ea

[PATCH v2] x86/centaur: report correct CPU/cache topology

Centaur CPUs enumerate the cache topology in the same way as Intel CPUs, but the functionality is unused so far. The Centaur init code also misses to initialize x86_info::max_cores, so the CPU topology can't be described correctly. Initialize x86_cpuinfo:max_core and invoke init_intel_cacheinfo()